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![Raghav Dogra](/assets/img/avatar_default.png)
This patch enables IFC NAND support on ARM layerscape platform. It fixes the dependency to enable NAND. The include files are being modified to ensure complilation for both PowerPC and ARM architectures. Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
338 lines
8.9 KiB
C
338 lines
8.9 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc
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*
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* Freescale Integrated Flash Controller
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*
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* Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/fsl_ifc.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
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EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
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/*
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* convert_ifc_address - convert the base address
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* @addr_base: base address of the memory bank
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*/
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unsigned int convert_ifc_address(phys_addr_t addr_base)
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{
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return addr_base & CSPR_BA;
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}
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EXPORT_SYMBOL(convert_ifc_address);
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/*
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* fsl_ifc_find - find IFC bank
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* @addr_base: base address of the memory bank
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*
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* This function walks IFC banks comparing "Base address" field of the CSPR
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* registers with the supplied addr_base argument. When bases match this
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* function returns bank number (starting with 0), otherwise it returns
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* appropriate errno value.
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*/
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int fsl_ifc_find(phys_addr_t addr_base)
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{
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int i = 0;
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if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
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return -ENODEV;
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for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
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u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
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if (cspr & CSPR_V && (cspr & CSPR_BA) ==
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convert_ifc_address(addr_base))
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return i;
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}
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return -ENOENT;
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}
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EXPORT_SYMBOL(fsl_ifc_find);
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static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
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{
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struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
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/*
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* Clear all the common status and event registers
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*/
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if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
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ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
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/* enable all error and events */
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ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);
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/* enable all error and event interrupts */
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ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
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ifc_out32(0x0, &ifc->cm_erattr0);
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ifc_out32(0x0, &ifc->cm_erattr1);
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return 0;
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}
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static int fsl_ifc_ctrl_remove(struct platform_device *dev)
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{
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struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
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free_irq(ctrl->nand_irq, ctrl);
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free_irq(ctrl->irq, ctrl);
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irq_dispose_mapping(ctrl->nand_irq);
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irq_dispose_mapping(ctrl->irq);
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iounmap(ctrl->gregs);
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dev_set_drvdata(&dev->dev, NULL);
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kfree(ctrl);
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return 0;
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}
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/*
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* NAND events are split between an operational interrupt which only
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* receives OPC, and an error interrupt that receives everything else,
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* including non-NAND errors. Whichever interrupt gets to it first
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* records the status and wakes the wait queue.
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*/
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static DEFINE_SPINLOCK(nand_irq_lock);
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static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
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{
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struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
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unsigned long flags;
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u32 stat;
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spin_lock_irqsave(&nand_irq_lock, flags);
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stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
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if (stat) {
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ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
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ctrl->nand_stat = stat;
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wake_up(&ctrl->nand_wait);
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}
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spin_unlock_irqrestore(&nand_irq_lock, flags);
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return stat;
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}
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static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
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{
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struct fsl_ifc_ctrl *ctrl = data;
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if (check_nand_stat(ctrl))
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return IRQ_HANDLED;
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return IRQ_NONE;
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}
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/*
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* NOTE: This interrupt is used to report ifc events of various kinds,
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* such as transaction errors on the chipselects.
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*/
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static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
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{
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struct fsl_ifc_ctrl *ctrl = data;
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struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
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u32 err_axiid, err_srcid, status, cs_err, err_addr;
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irqreturn_t ret = IRQ_NONE;
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/* read for chip select error */
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cs_err = ifc_in32(&ifc->cm_evter_stat);
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if (cs_err) {
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dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
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"any memory bank 0x%08X\n", cs_err);
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/* clear the chip select error */
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ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
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/* read error attribute registers print the error information */
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status = ifc_in32(&ifc->cm_erattr0);
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err_addr = ifc_in32(&ifc->cm_erattr1);
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if (status & IFC_CM_ERATTR0_ERTYP_READ)
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dev_err(ctrl->dev, "Read transaction error"
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"CM_ERATTR0 0x%08X\n", status);
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else
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dev_err(ctrl->dev, "Write transaction error"
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"CM_ERATTR0 0x%08X\n", status);
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err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
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IFC_CM_ERATTR0_ERAID_SHIFT;
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dev_err(ctrl->dev, "AXI ID of the error"
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"transaction 0x%08X\n", err_axiid);
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err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
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IFC_CM_ERATTR0_ESRCID_SHIFT;
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dev_err(ctrl->dev, "SRC ID of the error"
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"transaction 0x%08X\n", err_srcid);
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dev_err(ctrl->dev, "Transaction Address corresponding to error"
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"ERADDR 0x%08X\n", err_addr);
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ret = IRQ_HANDLED;
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}
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if (check_nand_stat(ctrl))
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ret = IRQ_HANDLED;
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return ret;
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}
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/*
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* fsl_ifc_ctrl_probe
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*
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* called by device layer when it finds a device matching
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* one our driver can handled. This code allocates all of
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* the resources needed for the controller only. The
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* resources for the NAND banks themselves are allocated
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* in the chip probe function.
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*/
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static int fsl_ifc_ctrl_probe(struct platform_device *dev)
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{
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int ret = 0;
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int version, banks;
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void __iomem *addr;
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dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
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fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
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if (!fsl_ifc_ctrl_dev)
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return -ENOMEM;
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dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
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/* IOMAP the entire IFC region */
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fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
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if (!fsl_ifc_ctrl_dev->gregs) {
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dev_err(&dev->dev, "failed to get memory region\n");
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ret = -ENODEV;
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goto err;
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}
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if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
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fsl_ifc_ctrl_dev->little_endian = true;
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dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
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} else {
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fsl_ifc_ctrl_dev->little_endian = false;
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dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
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}
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version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
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FSL_IFC_VERSION_MASK;
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banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
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dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
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version >> 24, (version >> 16) & 0xf, banks);
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fsl_ifc_ctrl_dev->version = version;
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fsl_ifc_ctrl_dev->banks = banks;
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addr = fsl_ifc_ctrl_dev->gregs;
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if (version >= FSL_IFC_VERSION_2_0_0)
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addr += PGOFFSET_64K;
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else
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addr += PGOFFSET_4K;
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fsl_ifc_ctrl_dev->rregs = addr;
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/* get the Controller level irq */
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fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
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if (fsl_ifc_ctrl_dev->irq == 0) {
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dev_err(&dev->dev, "failed to get irq resource "
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"for IFC\n");
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ret = -ENODEV;
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goto err;
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}
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/* get the nand machine irq */
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fsl_ifc_ctrl_dev->nand_irq =
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irq_of_parse_and_map(dev->dev.of_node, 1);
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fsl_ifc_ctrl_dev->dev = &dev->dev;
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ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
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if (ret < 0)
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goto err;
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init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
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ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
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"fsl-ifc", fsl_ifc_ctrl_dev);
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if (ret != 0) {
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dev_err(&dev->dev, "failed to install irq (%d)\n",
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fsl_ifc_ctrl_dev->irq);
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goto err_irq;
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}
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if (fsl_ifc_ctrl_dev->nand_irq) {
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ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
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0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
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if (ret != 0) {
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dev_err(&dev->dev, "failed to install irq (%d)\n",
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fsl_ifc_ctrl_dev->nand_irq);
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goto err_nandirq;
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}
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}
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return 0;
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err_nandirq:
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free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
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irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
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err_irq:
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free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
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irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
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err:
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return ret;
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}
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static const struct of_device_id fsl_ifc_match[] = {
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{
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.compatible = "fsl,ifc",
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},
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{},
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};
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static struct platform_driver fsl_ifc_ctrl_driver = {
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.driver = {
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.name = "fsl-ifc",
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.of_match_table = fsl_ifc_match,
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},
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.probe = fsl_ifc_ctrl_probe,
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.remove = fsl_ifc_ctrl_remove,
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};
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static int __init fsl_ifc_init(void)
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{
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return platform_driver_register(&fsl_ifc_ctrl_driver);
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}
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subsys_initcall(fsl_ifc_init);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Freescale Semiconductor");
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MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");
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