34 lines
1.0 KiB
C
34 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 - ARM Ltd
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*
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* stage2 page table helpers
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*/
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#ifndef __ARM64_S2_PGTABLE_H_
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#define __ARM64_S2_PGTABLE_H_
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#include <linux/pgtable.h>
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/*
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* The hardware supports concatenation of up to 16 tables at stage2 entry
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* level and we use the feature whenever possible, which means we resolve 4
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* additional bits of address at the entry level.
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*
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* This implies, the total number of page table levels required for
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* IPA_SHIFT at stage2 expected by the hardware can be calculated using
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* the same logic used for the (non-collapsable) stage1 page tables but for
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* (IPA_SHIFT - 4).
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*/
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#define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4)
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#define kvm_stage2_levels(mmu) VTCR_EL2_LVLS((mmu)->vtcr)
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/*
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* kvm_mmmu_cache_min_pages() is the number of pages required to install
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* a stage-2 translation. We pre-allocate the entry level page table at
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* the VM creation.
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*/
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#define kvm_mmu_cache_min_pages(mmu) (kvm_stage2_levels(mmu) - 1)
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#endif /* __ARM64_S2_PGTABLE_H_ */
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