336 lines
8.5 KiB
C
336 lines
8.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <hyp/switch.h>
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#include <linux/arm-smccc.h>
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#include <linux/kvm_host.h>
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#include <linux/types.h>
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#include <linux/jump_label.h>
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#include <linux/percpu.h>
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#include <uapi/linux/psci.h>
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#include <kvm/arm_psci.h>
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#include <asm/barrier.h>
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#include <asm/cpufeature.h>
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#include <asm/kprobes.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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#include <asm/fpsimd.h>
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#include <asm/debug-monitors.h>
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#include <asm/processor.h>
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#include <asm/thread_info.h>
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#include <asm/vectors.h>
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/* VHE specific context */
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DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
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DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
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DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
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static void __activate_traps(struct kvm_vcpu *vcpu)
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{
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u64 val;
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___activate_traps(vcpu);
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if (has_cntpoff()) {
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struct timer_map map;
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get_timer_map(vcpu, &map);
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/*
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* We're entrering the guest. Reload the correct
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* values from memory now that TGE is clear.
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*/
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if (map.direct_ptimer == vcpu_ptimer(vcpu))
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val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
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if (map.direct_ptimer == vcpu_hptimer(vcpu))
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val = __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2);
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if (map.direct_ptimer) {
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write_sysreg_el0(val, SYS_CNTP_CVAL);
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isb();
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}
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}
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val = read_sysreg(cpacr_el1);
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val |= CPACR_ELx_TTA;
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val &= ~(CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN |
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CPACR_EL1_SMEN_EL0EN | CPACR_EL1_SMEN_EL1EN);
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/*
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* With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
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* CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
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* except for some missing controls, such as TAM.
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* In this case, CPTR_EL2.TAM has the same position with or without
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* VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
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* shift value for trapping the AMU accesses.
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*/
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val |= CPTR_EL2_TAM;
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if (guest_owns_fp_regs(vcpu)) {
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if (vcpu_has_sve(vcpu))
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val |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN;
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} else {
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val &= ~(CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
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__activate_traps_fpsimd32(vcpu);
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}
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write_sysreg(val, cpacr_el1);
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write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1);
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}
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NOKPROBE_SYMBOL(__activate_traps);
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static void __deactivate_traps(struct kvm_vcpu *vcpu)
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{
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const char *host_vectors = vectors;
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___deactivate_traps(vcpu);
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2);
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if (has_cntpoff()) {
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struct timer_map map;
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u64 val, offset;
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get_timer_map(vcpu, &map);
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/*
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* We're exiting the guest. Save the latest CVAL value
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* to memory and apply the offset now that TGE is set.
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*/
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val = read_sysreg_el0(SYS_CNTP_CVAL);
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if (map.direct_ptimer == vcpu_ptimer(vcpu))
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__vcpu_sys_reg(vcpu, CNTP_CVAL_EL0) = val;
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if (map.direct_ptimer == vcpu_hptimer(vcpu))
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__vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2) = val;
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offset = read_sysreg_s(SYS_CNTPOFF_EL2);
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if (map.direct_ptimer && offset) {
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write_sysreg_el0(val + offset, SYS_CNTP_CVAL);
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isb();
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}
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}
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/*
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* ARM errata 1165522 and 1530923 require the actual execution of the
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* above before we can switch to the EL2/EL0 translation regime used by
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* the host.
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*/
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
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kvm_reset_cptr_el2(vcpu);
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if (!arm64_kernel_unmapped_at_el0())
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host_vectors = __this_cpu_read(this_cpu_vector);
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write_sysreg(host_vectors, vbar_el1);
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}
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NOKPROBE_SYMBOL(__deactivate_traps);
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/*
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* Disable IRQs in __vcpu_{load,put}_{activate,deactivate}_traps() to
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* prevent a race condition between context switching of PMUSERENR_EL0
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* in __{activate,deactivate}_traps_common() and IPIs that attempts to
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* update PMUSERENR_EL0. See also kvm_set_pmuserenr().
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*/
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static void __vcpu_load_activate_traps(struct kvm_vcpu *vcpu)
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{
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unsigned long flags;
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local_irq_save(flags);
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__activate_traps_common(vcpu);
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local_irq_restore(flags);
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}
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static void __vcpu_put_deactivate_traps(struct kvm_vcpu *vcpu)
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{
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unsigned long flags;
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local_irq_save(flags);
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__deactivate_traps_common(vcpu);
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local_irq_restore(flags);
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}
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void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu)
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{
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__vcpu_load_switch_sysregs(vcpu);
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__vcpu_load_activate_traps(vcpu);
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__load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch);
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}
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void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu)
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{
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__vcpu_put_deactivate_traps(vcpu);
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__vcpu_put_switch_sysregs(vcpu);
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}
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static const exit_handler_fn hyp_exit_handlers[] = {
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[0 ... ESR_ELx_EC_MAX] = NULL,
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[ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
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[ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg,
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[ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
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[ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
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[ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
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[ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
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[ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low,
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[ESR_ELx_EC_PAC] = kvm_hyp_handle_ptrauth,
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[ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops,
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};
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static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu)
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{
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return hyp_exit_handlers;
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}
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static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code)
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{
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/*
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* If we were in HYP context on entry, adjust the PSTATE view
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* so that the usual helpers work correctly.
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*/
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if (unlikely(vcpu_get_flag(vcpu, VCPU_HYP_CONTEXT))) {
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u64 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT);
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switch (mode) {
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case PSR_MODE_EL1t:
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mode = PSR_MODE_EL2t;
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break;
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case PSR_MODE_EL1h:
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mode = PSR_MODE_EL2h;
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break;
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}
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*vcpu_cpsr(vcpu) &= ~(PSR_MODE_MASK | PSR_MODE32_BIT);
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*vcpu_cpsr(vcpu) |= mode;
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}
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}
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/* Switch to the guest for VHE systems running in EL2 */
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static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpu_context *host_ctxt;
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struct kvm_cpu_context *guest_ctxt;
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u64 exit_code;
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host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
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host_ctxt->__hyp_running_vcpu = vcpu;
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guest_ctxt = &vcpu->arch.ctxt;
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sysreg_save_host_state_vhe(host_ctxt);
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/*
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* Note that ARM erratum 1165522 requires us to configure both stage 1
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* and stage 2 translation for the guest context before we clear
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* HCR_EL2.TGE. The stage 1 and stage 2 guest context has already been
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* loaded on the CPU in kvm_vcpu_load_vhe().
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*/
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__activate_traps(vcpu);
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__kvm_adjust_pc(vcpu);
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sysreg_restore_guest_state_vhe(guest_ctxt);
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__debug_switch_to_guest(vcpu);
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if (is_hyp_ctxt(vcpu))
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vcpu_set_flag(vcpu, VCPU_HYP_CONTEXT);
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else
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vcpu_clear_flag(vcpu, VCPU_HYP_CONTEXT);
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do {
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/* Jump in the fire! */
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exit_code = __guest_enter(vcpu);
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/* And we're baaack! */
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} while (fixup_guest_exit(vcpu, &exit_code));
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sysreg_save_guest_state_vhe(guest_ctxt);
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__deactivate_traps(vcpu);
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sysreg_restore_host_state_vhe(host_ctxt);
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if (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED)
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__fpsimd_save_fpexc32(vcpu);
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__debug_switch_to_host(vcpu);
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return exit_code;
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}
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NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
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int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
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{
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int ret;
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local_daif_mask();
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/*
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* Having IRQs masked via PMR when entering the guest means the GIC
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* will not signal the CPU of interrupts of lower priority, and the
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* only way to get out will be via guest exceptions.
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* Naturally, we want to avoid this.
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*
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* local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
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* dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
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*/
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pmr_sync();
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ret = __kvm_vcpu_run_vhe(vcpu);
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/*
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* local_daif_restore() takes care to properly restore PSTATE.DAIF
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* and the GIC PMR if the host is using IRQ priorities.
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*/
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local_daif_restore(DAIF_PROCCTX_NOIRQ);
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/*
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* When we exit from the guest we change a number of CPU configuration
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* parameters, such as traps. We rely on the isb() in kvm_call_hyp*()
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* to make sure these changes take effect before running the host or
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* additional guests.
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*/
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return ret;
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}
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static void __hyp_call_panic(u64 spsr, u64 elr, u64 par)
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{
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struct kvm_cpu_context *host_ctxt;
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struct kvm_vcpu *vcpu;
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host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
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vcpu = host_ctxt->__hyp_running_vcpu;
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__deactivate_traps(vcpu);
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sysreg_restore_host_state_vhe(host_ctxt);
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panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n",
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spsr, elr,
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read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR),
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read_sysreg(hpfar_el2), par, vcpu);
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}
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NOKPROBE_SYMBOL(__hyp_call_panic);
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void __noreturn hyp_panic(void)
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{
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u64 spsr = read_sysreg_el2(SYS_SPSR);
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u64 elr = read_sysreg_el2(SYS_ELR);
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u64 par = read_sysreg_par();
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__hyp_call_panic(spsr, elr, par);
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unreachable();
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}
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asmlinkage void kvm_unexpected_el2_exception(void)
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{
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__kvm_unexpected_el2_exception();
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}
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