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Ampere SoC PMU follows CoreSight PMU architecture. It uses implementation specific registers to filter events rather than PMEVFILTnR registers. Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Link: https://lore.kernel.org/r/20230913233941.9814-5-ilkka@os.amperecomputing.com [will: Include linux/io.h in ampere_cspmu.c for writel()] Signed-off-by: Will Deacon <will@kernel.org>
29 lines
1.1 KiB
Text
29 lines
1.1 KiB
Text
# SPDX-License-Identifier: GPL-2.0
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#
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# Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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config ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
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tristate "ARM Coresight Architecture PMU"
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depends on ARM64 || COMPILE_TEST
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help
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Provides support for performance monitoring unit (PMU) devices
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based on ARM CoreSight PMU architecture. Note that this PMU
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architecture does not have relationship with the ARM CoreSight
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Self-Hosted Tracing.
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config NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU
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tristate "NVIDIA Coresight Architecture PMU"
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depends on ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
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help
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Provides NVIDIA specific attributes for performance monitoring unit
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(PMU) devices based on ARM CoreSight PMU architecture.
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config AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU
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tristate "Ampere Coresight Architecture PMU"
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depends on ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
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help
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Provides Ampere specific attributes for performance monitoring unit
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(PMU) devices based on ARM CoreSight PMU architecture.
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In the first phase, the driver enables support on MCU PMU used in
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AmpereOne SoC family.
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