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642af0f92c
There exists several examples today of devices that embed an ethernet PHY or PCS directly inside an SoC. In this situation, either the device is controlled through a vendor-specific register set, or sometimes exposes the standard 802.3 registers that are typically accessed over MDIO. As phylib and phylink are designed to use mdiodevices, this driver allows creating a virtual MDIO bus, that translates mdiodev register accesses to regmap accesses. The reason we use regmap is because there are at least 3 such devices known today, 2 of them are Altera TSE PCS's, memory-mapped, exposed with a 4-byte stride in stmmac's dwmac-socfpga variant, and a 2-byte stride in altera-tse. The other one (nxp,sja1110-base-tx-mdio) is exposed over SPI. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
26 lines
586 B
C
26 lines
586 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Driver for MMIO-Mapped MDIO devices. Some IPs expose internal PHYs or PCS
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* within the MMIO-mapped area
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*
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* Copyright (C) 2023 Maxime Chevallier <maxime.chevallier@bootlin.com>
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*/
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#ifndef MDIO_REGMAP_H
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#define MDIO_REGMAP_H
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#include <linux/phy.h>
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struct device;
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struct regmap;
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struct mdio_regmap_config {
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struct device *parent;
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struct regmap *regmap;
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char name[MII_BUS_ID_SIZE];
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u8 valid_addr;
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bool autoscan;
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};
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struct mii_bus *devm_mdio_regmap_register(struct device *dev,
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const struct mdio_regmap_config *config);
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#endif
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