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17247821ae
In TI's reference manual description for the `AFE_Pen_Ctrl' bit-field
of the TSC's CTRL register, there is no mention of 8-wire touchscreens.
Even commit f0933a60d1 ("mfd: ti_am335x_tscadc: Update logic in CTRL
register for 5-wire TS") says that the value of this bit-field must be
the same for 4-wire and 8-wire touchscreens. So let's remove the
CNTRLREG_TSC_8WIRE macro to avoid misunderstandings.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211125224642.21011-5-dariobin@libero.it
196 lines
5.7 KiB
C
196 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* TI Touch Screen / ADC MFD driver
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
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#define __LINUX_TI_AM335X_TSCADC_MFD_H
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#include <linux/bitfield.h>
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#include <linux/mfd/core.h>
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#include <linux/units.h>
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#define REG_RAWIRQSTATUS 0x024
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#define REG_IRQSTATUS 0x028
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#define REG_IRQENABLE 0x02C
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#define REG_IRQCLR 0x030
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#define REG_IRQWAKEUP 0x034
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#define REG_DMAENABLE_SET 0x038
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#define REG_DMAENABLE_CLEAR 0x03c
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#define REG_CTRL 0x040
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#define REG_ADCFSM 0x044
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#define REG_CLKDIV 0x04C
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#define REG_SE 0x054
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#define REG_IDLECONFIG 0x058
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#define REG_CHARGECONFIG 0x05C
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#define REG_CHARGEDELAY 0x060
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#define REG_STEPCONFIG(n) (0x64 + ((n) * 8))
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#define REG_STEPDELAY(n) (0x68 + ((n) * 8))
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#define REG_FIFO0CNT 0xE4
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#define REG_FIFO0THR 0xE8
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#define REG_FIFO1CNT 0xF0
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#define REG_FIFO1THR 0xF4
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#define REG_DMA1REQ 0xF8
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#define REG_FIFO0 0x100
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#define REG_FIFO1 0x200
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/* Register Bitfields */
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/* IRQ wakeup enable */
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#define IRQWKUP_ENB BIT(0)
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/* IRQ enable */
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#define IRQENB_HW_PEN BIT(0)
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#define IRQENB_EOS BIT(1)
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#define IRQENB_FIFO0THRES BIT(2)
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#define IRQENB_FIFO0OVRRUN BIT(3)
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#define IRQENB_FIFO0UNDRFLW BIT(4)
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#define IRQENB_FIFO1THRES BIT(5)
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#define IRQENB_FIFO1OVRRUN BIT(6)
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#define IRQENB_FIFO1UNDRFLW BIT(7)
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#define IRQENB_PENUP BIT(9)
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/* Step Configuration */
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#define STEPCONFIG_MODE(val) FIELD_PREP(GENMASK(1, 0), (val))
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#define STEPCONFIG_MODE_SWCNT STEPCONFIG_MODE(1)
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#define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
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#define STEPCONFIG_AVG(val) FIELD_PREP(GENMASK(4, 2), (val))
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#define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4)
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#define STEPCONFIG_XPP BIT(5)
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#define STEPCONFIG_XNN BIT(6)
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#define STEPCONFIG_YPP BIT(7)
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#define STEPCONFIG_YNN BIT(8)
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#define STEPCONFIG_XNP BIT(9)
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#define STEPCONFIG_YPN BIT(10)
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#define STEPCONFIG_RFP(val) FIELD_PREP(GENMASK(13, 12), (val))
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#define STEPCONFIG_RFP_VREFP STEPCONFIG_RFP(3)
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#define STEPCONFIG_INM(val) FIELD_PREP(GENMASK(18, 15), (val))
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#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
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#define STEPCONFIG_INP(val) FIELD_PREP(GENMASK(22, 19), (val))
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#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
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#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
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#define STEPCONFIG_FIFO1 BIT(26)
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#define STEPCONFIG_RFM(val) FIELD_PREP(GENMASK(24, 23), (val))
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#define STEPCONFIG_RFM_VREFN STEPCONFIG_RFM(3)
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/* Delay register */
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#define STEPDELAY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val))
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#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
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#define STEPCONFIG_MAX_OPENDLY GENMASK(17, 0)
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#define STEPDELAY_SAMPLE(val) FIELD_PREP(GENMASK(31, 24), (val))
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#define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0)
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#define STEPCONFIG_MAX_SAMPLE GENMASK(7, 0)
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/* Charge Config */
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#define STEPCHARGE_RFP(val) FIELD_PREP(GENMASK(14, 12), (val))
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#define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
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#define STEPCHARGE_INM(val) FIELD_PREP(GENMASK(18, 15), (val))
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#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
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#define STEPCHARGE_INP(val) FIELD_PREP(GENMASK(22, 19), (val))
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#define STEPCHARGE_RFM(val) FIELD_PREP(GENMASK(24, 23), (val))
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#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
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/* Charge delay */
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#define CHARGEDLY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val))
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#define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(0x400)
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/* Control register */
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#define CNTRLREG_SSENB BIT(0)
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#define CNTRLREG_STEPID BIT(1)
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#define CNTRLREG_TSC_STEPCONFIGWRT BIT(2)
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#define CNTRLREG_POWERDOWN BIT(4)
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#define CNTRLREG_TSC_AFE_CTRL(val) FIELD_PREP(GENMASK(6, 5), (val))
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#define CNTRLREG_TSC_4WIRE CNTRLREG_TSC_AFE_CTRL(1)
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#define CNTRLREG_TSC_5WIRE CNTRLREG_TSC_AFE_CTRL(2)
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#define CNTRLREG_TSC_ENB BIT(7)
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/*Control registers bitfields for MAGADC IP */
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#define CNTRLREG_MAGADCENB BIT(0)
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#define CNTRLREG_MAG_PREAMP_PWRDOWN BIT(5)
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#define CNTRLREG_MAG_PREAMP_BYPASS BIT(6)
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/* FIFO READ Register */
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#define FIFOREAD_DATA_MASK GENMASK(11, 0)
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#define FIFOREAD_CHNLID_MASK GENMASK(19, 16)
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/* DMA ENABLE/CLEAR Register */
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#define DMA_FIFO0 BIT(0)
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#define DMA_FIFO1 BIT(1)
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/* Sequencer Status */
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#define SEQ_STATUS BIT(5)
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#define CHARGE_STEP 0x11
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#define TSC_ADC_CLK (3 * HZ_PER_MHZ)
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#define MAG_ADC_CLK (13 * HZ_PER_MHZ)
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#define TOTAL_STEPS 16
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#define TOTAL_CHANNELS 8
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#define FIFO1_THRESHOLD 19
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/*
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* time in us for processing a single channel, calculated as follows:
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*
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* max num cycles = open delay + (sample delay + conv time) * averaging
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*
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* max num cycles: 262143 + (255 + 13) * 16 = 266431
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*
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* clock frequency: 26MHz / 8 = 3.25MHz
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* clock period: 1 / 3.25MHz = 308ns
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*
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* max processing time: 266431 * 308ns = 83ms(approx)
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*/
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#define IDLE_TIMEOUT_MS 83 /* milliseconds */
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#define TSCADC_CELLS 2
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struct ti_tscadc_data {
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char *adc_feature_name;
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char *adc_feature_compatible;
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char *secondary_feature_name;
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char *secondary_feature_compatible;
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unsigned int target_clk_rate;
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};
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struct ti_tscadc_dev {
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struct device *dev;
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struct regmap *regmap;
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void __iomem *tscadc_base;
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phys_addr_t tscadc_phys_base;
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const struct ti_tscadc_data *data;
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int irq;
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struct mfd_cell cells[TSCADC_CELLS];
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u32 ctrl;
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u32 reg_se_cache;
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bool adc_waiting;
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bool adc_in_use;
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wait_queue_head_t reg_se_wait;
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spinlock_t reg_lock;
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unsigned int clk_div;
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/* tsc device */
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struct titsc *tsc;
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/* adc device */
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struct adc_device *adc;
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};
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static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
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{
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struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;
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return *tscadc_dev;
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}
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static inline bool ti_adc_with_touchscreen(struct ti_tscadc_dev *tscadc)
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{
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return of_device_is_compatible(tscadc->dev->of_node,
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"ti,am3359-tscadc");
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}
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void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
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void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
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void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
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void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc);
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#endif
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