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abd4627475
Based on the normalized pattern:
this program is free software you can redistribute it and/or modify it
under the terms of the gnu general public license version 2 as
published by the free software foundation this program is distributed
as is without any warranty of any kind whether expressed or implied
without even the implied warranty of merchantability or fitness for a
particular purpose see the gnu general public license version 2 for
more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
319 lines
9.5 KiB
C
319 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
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* Andrew F. Davis <afd@ti.com>
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*
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* Based on the TPS65218 driver and the previous TPS65912 driver by
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* Margarita Olaya Cabrera <magi@slimlogic.co.uk>
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*/
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#ifndef __LINUX_MFD_TPS65912_H
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#define __LINUX_MFD_TPS65912_H
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#include <linux/device.h>
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#include <linux/regmap.h>
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/* List of registers for TPS65912 */
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#define TPS65912_DCDC1_CTRL 0x00
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#define TPS65912_DCDC2_CTRL 0x01
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#define TPS65912_DCDC3_CTRL 0x02
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#define TPS65912_DCDC4_CTRL 0x03
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#define TPS65912_DCDC1_OP 0x04
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#define TPS65912_DCDC1_AVS 0x05
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#define TPS65912_DCDC1_LIMIT 0x06
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#define TPS65912_DCDC2_OP 0x07
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#define TPS65912_DCDC2_AVS 0x08
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#define TPS65912_DCDC2_LIMIT 0x09
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#define TPS65912_DCDC3_OP 0x0A
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#define TPS65912_DCDC3_AVS 0x0B
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#define TPS65912_DCDC3_LIMIT 0x0C
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#define TPS65912_DCDC4_OP 0x0D
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#define TPS65912_DCDC4_AVS 0x0E
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#define TPS65912_DCDC4_LIMIT 0x0F
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#define TPS65912_LDO1_OP 0x10
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#define TPS65912_LDO1_AVS 0x11
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#define TPS65912_LDO1_LIMIT 0x12
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#define TPS65912_LDO2_OP 0x13
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#define TPS65912_LDO2_AVS 0x14
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#define TPS65912_LDO2_LIMIT 0x15
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#define TPS65912_LDO3_OP 0x16
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#define TPS65912_LDO3_AVS 0x17
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#define TPS65912_LDO3_LIMIT 0x18
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#define TPS65912_LDO4_OP 0x19
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#define TPS65912_LDO4_AVS 0x1A
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#define TPS65912_LDO4_LIMIT 0x1B
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#define TPS65912_LDO5 0x1C
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#define TPS65912_LDO6 0x1D
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#define TPS65912_LDO7 0x1E
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#define TPS65912_LDO8 0x1F
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#define TPS65912_LDO9 0x20
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#define TPS65912_LDO10 0x21
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#define TPS65912_THRM 0x22
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#define TPS65912_CLK32OUT 0x23
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#define TPS65912_DEVCTRL 0x24
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#define TPS65912_DEVCTRL2 0x25
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#define TPS65912_I2C_SPI_CFG 0x26
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#define TPS65912_KEEP_ON 0x27
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#define TPS65912_KEEP_ON2 0x28
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#define TPS65912_SET_OFF1 0x29
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#define TPS65912_SET_OFF2 0x2A
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#define TPS65912_DEF_VOLT 0x2B
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#define TPS65912_DEF_VOLT_MAPPING 0x2C
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#define TPS65912_DISCHARGE 0x2D
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#define TPS65912_DISCHARGE2 0x2E
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#define TPS65912_EN1_SET1 0x2F
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#define TPS65912_EN1_SET2 0x30
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#define TPS65912_EN2_SET1 0x31
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#define TPS65912_EN2_SET2 0x32
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#define TPS65912_EN3_SET1 0x33
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#define TPS65912_EN3_SET2 0x34
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#define TPS65912_EN4_SET1 0x35
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#define TPS65912_EN4_SET2 0x36
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#define TPS65912_PGOOD 0x37
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#define TPS65912_PGOOD2 0x38
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#define TPS65912_INT_STS 0x39
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#define TPS65912_INT_MSK 0x3A
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#define TPS65912_INT_STS2 0x3B
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#define TPS65912_INT_MSK2 0x3C
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#define TPS65912_INT_STS3 0x3D
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#define TPS65912_INT_MSK3 0x3E
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#define TPS65912_INT_STS4 0x3F
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#define TPS65912_INT_MSK4 0x40
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#define TPS65912_GPIO1 0x41
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#define TPS65912_GPIO2 0x42
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#define TPS65912_GPIO3 0x43
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#define TPS65912_GPIO4 0x44
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#define TPS65912_GPIO5 0x45
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#define TPS65912_VMON 0x46
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#define TPS65912_LEDA_CTRL1 0x47
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#define TPS65912_LEDA_CTRL2 0x48
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#define TPS65912_LEDA_CTRL3 0x49
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#define TPS65912_LEDA_CTRL4 0x4A
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#define TPS65912_LEDA_CTRL5 0x4B
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#define TPS65912_LEDA_CTRL6 0x4C
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#define TPS65912_LEDA_CTRL7 0x4D
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#define TPS65912_LEDA_CTRL8 0x4E
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#define TPS65912_LEDB_CTRL1 0x4F
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#define TPS65912_LEDB_CTRL2 0x50
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#define TPS65912_LEDB_CTRL3 0x51
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#define TPS65912_LEDB_CTRL4 0x52
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#define TPS65912_LEDB_CTRL5 0x53
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#define TPS65912_LEDB_CTRL6 0x54
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#define TPS65912_LEDB_CTRL7 0x55
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#define TPS65912_LEDB_CTRL8 0x56
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#define TPS65912_LEDC_CTRL1 0x57
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#define TPS65912_LEDC_CTRL2 0x58
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#define TPS65912_LEDC_CTRL3 0x59
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#define TPS65912_LEDC_CTRL4 0x5A
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#define TPS65912_LEDC_CTRL5 0x5B
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#define TPS65912_LEDC_CTRL6 0x5C
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#define TPS65912_LEDC_CTRL7 0x5D
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#define TPS65912_LEDC_CTRL8 0x5E
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#define TPS65912_LED_RAMP_UP_TIME 0x5F
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#define TPS65912_LED_RAMP_DOWN_TIME 0x60
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#define TPS65912_LED_SEQ_EN 0x61
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#define TPS65912_LOADSWITCH 0x62
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#define TPS65912_SPARE 0x63
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#define TPS65912_VERNUM 0x64
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#define TPS6591X_MAX_REGISTER 0x64
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/* INT_STS Register field definitions */
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#define TPS65912_INT_STS_PWRHOLD_F BIT(0)
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#define TPS65912_INT_STS_VMON BIT(1)
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#define TPS65912_INT_STS_PWRON BIT(2)
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#define TPS65912_INT_STS_PWRON_LP BIT(3)
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#define TPS65912_INT_STS_PWRHOLD_R BIT(4)
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#define TPS65912_INT_STS_HOTDIE BIT(5)
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#define TPS65912_INT_STS_GPIO1_R BIT(6)
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#define TPS65912_INT_STS_GPIO1_F BIT(7)
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/* INT_STS Register field definitions */
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#define TPS65912_INT_STS2_GPIO2_R BIT(0)
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#define TPS65912_INT_STS2_GPIO2_F BIT(1)
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#define TPS65912_INT_STS2_GPIO3_R BIT(2)
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#define TPS65912_INT_STS2_GPIO3_F BIT(3)
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#define TPS65912_INT_STS2_GPIO4_R BIT(4)
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#define TPS65912_INT_STS2_GPIO4_F BIT(5)
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#define TPS65912_INT_STS2_GPIO5_R BIT(6)
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#define TPS65912_INT_STS2_GPIO5_F BIT(7)
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/* INT_STS Register field definitions */
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#define TPS65912_INT_STS3_PGOOD_DCDC1 BIT(0)
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#define TPS65912_INT_STS3_PGOOD_DCDC2 BIT(1)
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#define TPS65912_INT_STS3_PGOOD_DCDC3 BIT(2)
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#define TPS65912_INT_STS3_PGOOD_DCDC4 BIT(3)
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#define TPS65912_INT_STS3_PGOOD_LDO1 BIT(4)
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#define TPS65912_INT_STS3_PGOOD_LDO2 BIT(5)
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#define TPS65912_INT_STS3_PGOOD_LDO3 BIT(6)
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#define TPS65912_INT_STS3_PGOOD_LDO4 BIT(7)
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/* INT_STS Register field definitions */
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#define TPS65912_INT_STS4_PGOOD_LDO5 BIT(0)
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#define TPS65912_INT_STS4_PGOOD_LDO6 BIT(1)
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#define TPS65912_INT_STS4_PGOOD_LDO7 BIT(2)
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#define TPS65912_INT_STS4_PGOOD_LDO8 BIT(3)
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#define TPS65912_INT_STS4_PGOOD_LDO9 BIT(4)
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#define TPS65912_INT_STS4_PGOOD_LDO10 BIT(5)
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/* GPIO 1 and 2 Register field definitions */
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#define GPIO_SLEEP_MASK 0x80
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#define GPIO_SLEEP_SHIFT 7
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#define GPIO_DEB_MASK 0x10
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#define GPIO_DEB_SHIFT 4
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#define GPIO_CFG_MASK 0x04
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#define GPIO_CFG_SHIFT 2
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#define GPIO_STS_MASK 0x02
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#define GPIO_STS_SHIFT 1
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#define GPIO_SET_MASK 0x01
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#define GPIO_SET_SHIFT 0
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/* GPIO 3 Register field definitions */
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#define GPIO3_SLEEP_MASK 0x80
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#define GPIO3_SLEEP_SHIFT 7
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#define GPIO3_SEL_MASK 0x40
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#define GPIO3_SEL_SHIFT 6
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#define GPIO3_ODEN_MASK 0x20
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#define GPIO3_ODEN_SHIFT 5
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#define GPIO3_DEB_MASK 0x10
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#define GPIO3_DEB_SHIFT 4
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#define GPIO3_PDEN_MASK 0x08
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#define GPIO3_PDEN_SHIFT 3
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#define GPIO3_CFG_MASK 0x04
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#define GPIO3_CFG_SHIFT 2
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#define GPIO3_STS_MASK 0x02
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#define GPIO3_STS_SHIFT 1
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#define GPIO3_SET_MASK 0x01
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#define GPIO3_SET_SHIFT 0
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/* GPIO 4 Register field definitions */
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#define GPIO4_SLEEP_MASK 0x80
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#define GPIO4_SLEEP_SHIFT 7
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#define GPIO4_SEL_MASK 0x40
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#define GPIO4_SEL_SHIFT 6
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#define GPIO4_ODEN_MASK 0x20
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#define GPIO4_ODEN_SHIFT 5
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#define GPIO4_DEB_MASK 0x10
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#define GPIO4_DEB_SHIFT 4
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#define GPIO4_PDEN_MASK 0x08
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#define GPIO4_PDEN_SHIFT 3
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#define GPIO4_CFG_MASK 0x04
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#define GPIO4_CFG_SHIFT 2
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#define GPIO4_STS_MASK 0x02
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#define GPIO4_STS_SHIFT 1
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#define GPIO4_SET_MASK 0x01
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#define GPIO4_SET_SHIFT 0
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/* Register THERM (0x80) register.RegisterDescription */
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#define THERM_THERM_HD_MASK 0x20
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#define THERM_THERM_HD_SHIFT 5
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#define THERM_THERM_TS_MASK 0x10
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#define THERM_THERM_TS_SHIFT 4
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#define THERM_THERM_HDSEL_MASK 0x0C
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#define THERM_THERM_HDSEL_SHIFT 2
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#define THERM_RSVD1_MASK 0x02
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#define THERM_RSVD1_SHIFT 1
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#define THERM_THERM_STATE_MASK 0x01
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#define THERM_THERM_STATE_SHIFT 0
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/* Register DCDCCTRL1 register.RegisterDescription */
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#define DCDCCTRL_VCON_ENABLE_MASK 0x80
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#define DCDCCTRL_VCON_ENABLE_SHIFT 7
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#define DCDCCTRL_VCON_RANGE1_MASK 0x40
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#define DCDCCTRL_VCON_RANGE1_SHIFT 6
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#define DCDCCTRL_VCON_RANGE0_MASK 0x20
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#define DCDCCTRL_VCON_RANGE0_SHIFT 5
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#define DCDCCTRL_TSTEP2_MASK 0x10
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#define DCDCCTRL_TSTEP2_SHIFT 4
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#define DCDCCTRL_TSTEP1_MASK 0x08
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#define DCDCCTRL_TSTEP1_SHIFT 3
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#define DCDCCTRL_TSTEP0_MASK 0x04
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#define DCDCCTRL_TSTEP0_SHIFT 2
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#define DCDCCTRL_DCDC1_MODE_MASK 0x02
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#define DCDCCTRL_DCDC1_MODE_SHIFT 1
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/* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */
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#define DCDCCTRL_TSTEP2_MASK 0x10
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#define DCDCCTRL_TSTEP2_SHIFT 4
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#define DCDCCTRL_TSTEP1_MASK 0x08
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#define DCDCCTRL_TSTEP1_SHIFT 3
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#define DCDCCTRL_TSTEP0_MASK 0x04
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#define DCDCCTRL_TSTEP0_SHIFT 2
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#define DCDCCTRL_DCDC_MODE_MASK 0x02
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#define DCDCCTRL_DCDC_MODE_SHIFT 1
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#define DCDCCTRL_RSVD0_MASK 0x01
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#define DCDCCTRL_RSVD0_SHIFT 0
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/* Register DCDCCTRL4 register.RegisterDescription */
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#define DCDCCTRL_RAMP_TIME_MASK 0x01
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#define DCDCCTRL_RAMP_TIME_SHIFT 0
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/* Register DCDCx_AVS */
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#define DCDC_AVS_ENABLE_MASK 0x80
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#define DCDC_AVS_ENABLE_SHIFT 7
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#define DCDC_AVS_ECO_MASK 0x40
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#define DCDC_AVS_ECO_SHIFT 6
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/* Register DCDCx_LIMIT */
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#define DCDC_LIMIT_RANGE_MASK 0xC0
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#define DCDC_LIMIT_RANGE_SHIFT 6
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#define DCDC_LIMIT_MAX_SEL_MASK 0x3F
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#define DCDC_LIMIT_MAX_SEL_SHIFT 0
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/* Define the TPS65912 IRQ numbers */
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enum tps65912_irqs {
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/* INT_STS registers */
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TPS65912_IRQ_PWRHOLD_F,
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TPS65912_IRQ_VMON,
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TPS65912_IRQ_PWRON,
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TPS65912_IRQ_PWRON_LP,
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TPS65912_IRQ_PWRHOLD_R,
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TPS65912_IRQ_HOTDIE,
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TPS65912_IRQ_GPIO1_R,
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TPS65912_IRQ_GPIO1_F,
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/* INT_STS2 registers */
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TPS65912_IRQ_GPIO2_R,
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TPS65912_IRQ_GPIO2_F,
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TPS65912_IRQ_GPIO3_R,
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TPS65912_IRQ_GPIO3_F,
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TPS65912_IRQ_GPIO4_R,
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TPS65912_IRQ_GPIO4_F,
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TPS65912_IRQ_GPIO5_R,
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TPS65912_IRQ_GPIO5_F,
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/* INT_STS3 registers */
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TPS65912_IRQ_PGOOD_DCDC1,
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TPS65912_IRQ_PGOOD_DCDC2,
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TPS65912_IRQ_PGOOD_DCDC3,
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TPS65912_IRQ_PGOOD_DCDC4,
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TPS65912_IRQ_PGOOD_LDO1,
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TPS65912_IRQ_PGOOD_LDO2,
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TPS65912_IRQ_PGOOD_LDO3,
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TPS65912_IRQ_PGOOD_LDO4,
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/* INT_STS4 registers */
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TPS65912_IRQ_PGOOD_LDO5,
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TPS65912_IRQ_PGOOD_LDO6,
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TPS65912_IRQ_PGOOD_LDO7,
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TPS65912_IRQ_PGOOD_LDO8,
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TPS65912_IRQ_PGOOD_LDO9,
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TPS65912_IRQ_PGOOD_LDO10,
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};
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/*
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* struct tps65912 - state holder for the tps65912 driver
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*
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* Device data may be used to access the TPS65912 chip
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*/
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struct tps65912 {
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struct device *dev;
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struct regmap *regmap;
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/* IRQ Data */
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int irq;
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struct regmap_irq_chip_data *irq_data;
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};
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extern const struct regmap_config tps65912_regmap_config;
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int tps65912_device_init(struct tps65912 *tps);
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void tps65912_device_exit(struct tps65912 *tps);
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#endif /* __LINUX_MFD_TPS65912_H */
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