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08c6d8bae4
The KSZ9477 errata points out (in 'Module 4') the link up/down problems
when EEE (Energy Efficient Ethernet) is enabled in the device to which
the KSZ9477 tries to auto negotiate.
The suggested workaround is to clear advertisement of EEE for PHYs in
this chip driver.
To avoid regressions with other switch ICs the new MICREL_NO_EEE flag
has been introduced.
Moreover, the in-register disablement of MMD_DEVICE_ID_EEE_ADV.MMD_EEE_ADV
MMD register is removed, as this code is both; now executed too late
(after previous rework of the PHY and DSA for KSZ switches) and not
required as setting all members of eee_broken_modes bit field prevents
the KSZ9477 from advertising EEE.
Fixes: 69d3b36ca0 ("net: dsa: microchip: enable EEE support") # for KSZ9477
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Oleksij Rempel <o.rempel@pengutronix.de> # Confirmed disabled EEE with oscilloscope.
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20230905093315.784052-1-lukma@denx.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
69 lines
2 KiB
C
69 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* include/linux/micrel_phy.h
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*
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* Micrel PHY IDs
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*/
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#ifndef _MICREL_PHY_H
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#define _MICREL_PHY_H
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#define MICREL_OUI 0x0885
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#define MICREL_PHY_ID_MASK 0x00fffff0
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#define PHY_ID_KSZ8873MLL 0x000e7237
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#define PHY_ID_KSZ9021 0x00221610
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#define PHY_ID_KSZ9021RLRN 0x00221611
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#define PHY_ID_KS8737 0x00221720
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#define PHY_ID_KSZ8021 0x00221555
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#define PHY_ID_KSZ8031 0x00221556
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#define PHY_ID_KSZ8041 0x00221510
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/* undocumented */
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#define PHY_ID_KSZ8041RNLI 0x00221537
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#define PHY_ID_KSZ8051 0x00221550
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/* same id: ks8001 Rev. A/B, and ks8721 Rev 3. */
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#define PHY_ID_KSZ8001 0x0022161A
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/* same id: KS8081, KS8091 */
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#define PHY_ID_KSZ8081 0x00221560
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#define PHY_ID_KSZ8061 0x00221570
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#define PHY_ID_KSZ9031 0x00221620
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#define PHY_ID_KSZ9131 0x00221640
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#define PHY_ID_LAN8814 0x00221660
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#define PHY_ID_LAN8804 0x00221670
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#define PHY_ID_LAN8841 0x00221650
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#define PHY_ID_KSZ886X 0x00221430
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#define PHY_ID_KSZ8863 0x00221435
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#define PHY_ID_KSZ87XX 0x00221550
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#define PHY_ID_KSZ9477 0x00221631
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/* struct phy_device dev_flags definitions */
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#define MICREL_PHY_50MHZ_CLK BIT(0)
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#define MICREL_PHY_FXEN BIT(1)
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#define MICREL_KSZ8_P1_ERRATA BIT(2)
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#define MICREL_NO_EEE BIT(3)
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#define MICREL_KSZ9021_EXTREG_CTRL 0xB
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#define MICREL_KSZ9021_EXTREG_DATA_WRITE 0xC
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#define MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW 0x104
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#define MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW 0x105
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/* Device specific MII_BMCR (Reg 0) bits */
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/* 1 = HP Auto MDI/MDI-X mode, 0 = Microchip Auto MDI/MDI-X mode */
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#define KSZ886X_BMCR_HP_MDIX BIT(5)
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/* 1 = Force MDI (transmit on RXP/RXM pins), 0 = Normal operation
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* (transmit on TXP/TXM pins)
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*/
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#define KSZ886X_BMCR_FORCE_MDI BIT(4)
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/* 1 = Disable auto MDI-X */
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#define KSZ886X_BMCR_DISABLE_AUTO_MDIX BIT(3)
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#define KSZ886X_BMCR_DISABLE_FAR_END_FAULT BIT(2)
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#define KSZ886X_BMCR_DISABLE_TRANSMIT BIT(1)
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#define KSZ886X_BMCR_DISABLE_LED BIT(0)
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#define KSZ886X_CTRL_MDIX_STAT BIT(4)
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#endif /* _MICREL_PHY_H */
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