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83c5e13b8c
Provide all the necessary bits in the generic riscv pmu driver to be able to mmap perf events in userspace: the heavy lifting lies in the driver backend, namely the legacy and sbi implementations. Note that arch_perf_update_userpage is almost a copy of arm64 code. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com>
88 lines
2.6 KiB
C
88 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 SiFive
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* Copyright (C) 2018 Andes Technology Corporation
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* Copyright (C) 2021 Western Digital Corporation or its affiliates.
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*
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*/
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#ifndef _RISCV_PMU_H
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#define _RISCV_PMU_H
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#include <linux/perf_event.h>
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#include <linux/ptrace.h>
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#include <linux/interrupt.h>
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#ifdef CONFIG_RISCV_PMU
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/*
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* The RISCV_MAX_COUNTERS parameter should be specified.
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*/
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#define RISCV_MAX_COUNTERS 64
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#define RISCV_OP_UNSUPP (-EOPNOTSUPP)
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#define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi"
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#define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy"
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#define RISCV_PMU_STOP_FLAG_RESET 1
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#define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1
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struct cpu_hw_events {
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/* currently enabled events */
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int n_events;
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/* Counter overflow interrupt */
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int irq;
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/* currently enabled events */
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struct perf_event *events[RISCV_MAX_COUNTERS];
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/* currently enabled hardware counters */
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DECLARE_BITMAP(used_hw_ctrs, RISCV_MAX_COUNTERS);
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/* currently enabled firmware counters */
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DECLARE_BITMAP(used_fw_ctrs, RISCV_MAX_COUNTERS);
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};
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struct riscv_pmu {
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struct pmu pmu;
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char *name;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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unsigned long cmask;
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u64 (*ctr_read)(struct perf_event *event);
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int (*ctr_get_idx)(struct perf_event *event);
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int (*ctr_get_width)(int idx);
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void (*ctr_clear_idx)(struct perf_event *event);
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void (*ctr_start)(struct perf_event *event, u64 init_val);
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void (*ctr_stop)(struct perf_event *event, unsigned long flag);
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int (*event_map)(struct perf_event *event, u64 *config);
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void (*event_init)(struct perf_event *event);
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void (*event_mapped)(struct perf_event *event, struct mm_struct *mm);
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void (*event_unmapped)(struct perf_event *event, struct mm_struct *mm);
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uint8_t (*csr_index)(struct perf_event *event);
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struct cpu_hw_events __percpu *hw_events;
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struct hlist_node node;
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struct notifier_block riscv_pm_nb;
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};
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#define to_riscv_pmu(p) (container_of(p, struct riscv_pmu, pmu))
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void riscv_pmu_start(struct perf_event *event, int flags);
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void riscv_pmu_stop(struct perf_event *event, int flags);
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unsigned long riscv_pmu_ctr_read_csr(unsigned long csr);
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int riscv_pmu_event_set_period(struct perf_event *event);
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uint64_t riscv_pmu_ctr_get_width_mask(struct perf_event *event);
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u64 riscv_pmu_event_update(struct perf_event *event);
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#ifdef CONFIG_RISCV_PMU_LEGACY
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void riscv_pmu_legacy_skip_init(void);
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#else
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static inline void riscv_pmu_legacy_skip_init(void) {};
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#endif
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struct riscv_pmu *riscv_pmu_alloc(void);
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#ifdef CONFIG_RISCV_PMU_SBI
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int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr);
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#endif
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#endif /* CONFIG_RISCV_PMU */
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#endif /* _RISCV_PMU_H */
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