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![Babu Moger](/assets/img/avatar_default.png)
The event configuration for mbm_total_bytes can be changed by the user by
writing to the file /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config.
The event configuration settings are domain specific and affect all the
CPUs in the domain.
Following are the types of events supported:
==== ===========================================================
Bits Description
==== ===========================================================
6 Dirty Victims from the QOS domain to all types of memory
5 Reads to slow memory in the non-local NUMA domain
4 Reads to slow memory in the local NUMA domain
3 Non-temporal writes to non-local NUMA domain
2 Non-temporal writes to local NUMA domain
1 Reads to memory in the non-local NUMA domain
0 Reads to memory in the local NUMA domain
==== ===========================================================
For example:
To change the mbm_total_bytes to count only reads on domain 0, the bits
0, 1, 4 and 5 needs to be set, which is 110011b (in hex 0x33).
Run the command:
$echo 0=0x33 > /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config
To change the mbm_total_bytes to count all the slow memory reads on domain 1,
the bits 4 and 5 needs to be set which is 110000b
(in hex 0x30).
Run the command:
$echo 1=0x30 > /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config
Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://lore.kernel.org/r/20230113152039.770054-12-babu.moger@amd.com
267 lines
8.7 KiB
C
267 lines
8.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _RESCTRL_H
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#define _RESCTRL_H
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/pid.h>
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#ifdef CONFIG_PROC_CPU_RESCTRL
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int proc_resctrl_show(struct seq_file *m,
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struct pid_namespace *ns,
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struct pid *pid,
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struct task_struct *tsk);
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#endif
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/* max value for struct rdt_domain's mbps_val */
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#define MBA_MAX_MBPS U32_MAX
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/**
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* enum resctrl_conf_type - The type of configuration.
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* @CDP_NONE: No prioritisation, both code and data are controlled or monitored.
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* @CDP_CODE: Configuration applies to instruction fetches.
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* @CDP_DATA: Configuration applies to reads and writes.
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*/
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enum resctrl_conf_type {
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CDP_NONE,
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CDP_CODE,
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CDP_DATA,
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};
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#define CDP_NUM_TYPES (CDP_DATA + 1)
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/*
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* Event IDs, the values match those used to program IA32_QM_EVTSEL before
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* reading IA32_QM_CTR on RDT systems.
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*/
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enum resctrl_event_id {
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QOS_L3_OCCUP_EVENT_ID = 0x01,
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QOS_L3_MBM_TOTAL_EVENT_ID = 0x02,
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QOS_L3_MBM_LOCAL_EVENT_ID = 0x03,
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};
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/**
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* struct resctrl_staged_config - parsed configuration to be applied
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* @new_ctrl: new ctrl value to be loaded
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* @have_new_ctrl: whether the user provided new_ctrl is valid
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*/
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struct resctrl_staged_config {
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u32 new_ctrl;
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bool have_new_ctrl;
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};
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/**
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* struct rdt_domain - group of CPUs sharing a resctrl resource
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* @list: all instances of this resource
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* @id: unique id for this instance
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* @cpu_mask: which CPUs share this resource
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* @rmid_busy_llc: bitmap of which limbo RMIDs are above threshold
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* @mbm_total: saved state for MBM total bandwidth
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* @mbm_local: saved state for MBM local bandwidth
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* @mbm_over: worker to periodically read MBM h/w counters
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* @cqm_limbo: worker to periodically read CQM h/w counters
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* @mbm_work_cpu: worker CPU for MBM h/w counters
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* @cqm_work_cpu: worker CPU for CQM h/w counters
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* @plr: pseudo-locked region (if any) associated with domain
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* @staged_config: parsed configuration to be applied
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* @mbps_val: When mba_sc is enabled, this holds the array of user
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* specified control values for mba_sc in MBps, indexed
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* by closid
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*/
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struct rdt_domain {
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struct list_head list;
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int id;
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struct cpumask cpu_mask;
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unsigned long *rmid_busy_llc;
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struct mbm_state *mbm_total;
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struct mbm_state *mbm_local;
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struct delayed_work mbm_over;
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struct delayed_work cqm_limbo;
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int mbm_work_cpu;
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int cqm_work_cpu;
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struct pseudo_lock_region *plr;
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struct resctrl_staged_config staged_config[CDP_NUM_TYPES];
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u32 *mbps_val;
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};
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/**
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* struct resctrl_cache - Cache allocation related data
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* @cbm_len: Length of the cache bit mask
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* @min_cbm_bits: Minimum number of consecutive bits to be set.
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* The value 0 means the architecture can support
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* zero CBM.
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* @shareable_bits: Bitmask of shareable resource with other
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* executing entities
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* @arch_has_sparse_bitmaps: True if a bitmap like f00f is valid.
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* @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache
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* level has CPU scope.
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*/
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struct resctrl_cache {
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unsigned int cbm_len;
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unsigned int min_cbm_bits;
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unsigned int shareable_bits;
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bool arch_has_sparse_bitmaps;
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bool arch_has_per_cpu_cfg;
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};
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/**
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* enum membw_throttle_mode - System's memory bandwidth throttling mode
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* @THREAD_THROTTLE_UNDEFINED: Not relevant to the system
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* @THREAD_THROTTLE_MAX: Memory bandwidth is throttled at the core
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* always using smallest bandwidth percentage
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* assigned to threads, aka "max throttling"
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* @THREAD_THROTTLE_PER_THREAD: Memory bandwidth is throttled at the thread
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*/
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enum membw_throttle_mode {
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THREAD_THROTTLE_UNDEFINED = 0,
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THREAD_THROTTLE_MAX,
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THREAD_THROTTLE_PER_THREAD,
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};
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/**
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* struct resctrl_membw - Memory bandwidth allocation related data
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* @min_bw: Minimum memory bandwidth percentage user can request
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* @bw_gran: Granularity at which the memory bandwidth is allocated
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* @delay_linear: True if memory B/W delay is in linear scale
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* @arch_needs_linear: True if we can't configure non-linear resources
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* @throttle_mode: Bandwidth throttling mode when threads request
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* different memory bandwidths
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* @mba_sc: True if MBA software controller(mba_sc) is enabled
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* @mb_map: Mapping of memory B/W percentage to memory B/W delay
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*/
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struct resctrl_membw {
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u32 min_bw;
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u32 bw_gran;
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u32 delay_linear;
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bool arch_needs_linear;
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enum membw_throttle_mode throttle_mode;
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bool mba_sc;
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u32 *mb_map;
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};
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struct rdt_parse_data;
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struct resctrl_schema;
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/**
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* struct rdt_resource - attributes of a resctrl resource
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* @rid: The index of the resource
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* @alloc_capable: Is allocation available on this machine
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* @mon_capable: Is monitor feature available on this machine
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* @num_rmid: Number of RMIDs available
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* @cache_level: Which cache level defines scope of this resource
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* @cache: Cache allocation related data
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* @membw: If the component has bandwidth controls, their properties.
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* @domains: All domains for this resource
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* @name: Name to use in "schemata" file.
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* @data_width: Character width of data when displaying
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* @default_ctrl: Specifies default cache cbm or memory B/W percent.
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* @format_str: Per resource format string to show domain value
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* @parse_ctrlval: Per resource function pointer to parse control values
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* @evt_list: List of monitoring events
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* @fflags: flags to choose base and info files
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* @cdp_capable: Is the CDP feature available on this resource
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*/
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struct rdt_resource {
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int rid;
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bool alloc_capable;
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bool mon_capable;
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int num_rmid;
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int cache_level;
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struct resctrl_cache cache;
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struct resctrl_membw membw;
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struct list_head domains;
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char *name;
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int data_width;
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u32 default_ctrl;
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const char *format_str;
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int (*parse_ctrlval)(struct rdt_parse_data *data,
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struct resctrl_schema *s,
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struct rdt_domain *d);
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struct list_head evt_list;
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unsigned long fflags;
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bool cdp_capable;
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};
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/**
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* struct resctrl_schema - configuration abilities of a resource presented to
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* user-space
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* @list: Member of resctrl_schema_all.
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* @name: The name to use in the "schemata" file.
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* @conf_type: Whether this schema is specific to code/data.
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* @res: The resource structure exported by the architecture to describe
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* the hardware that is configured by this schema.
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* @num_closid: The number of closid that can be used with this schema. When
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* features like CDP are enabled, this will be lower than the
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* hardware supports for the resource.
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*/
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struct resctrl_schema {
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struct list_head list;
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char name[8];
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enum resctrl_conf_type conf_type;
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struct rdt_resource *res;
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u32 num_closid;
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};
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/* The number of closid supported by this resource regardless of CDP */
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u32 resctrl_arch_get_num_closid(struct rdt_resource *r);
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int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid);
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/*
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* Update the ctrl_val and apply this config right now.
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* Must be called on one of the domain's CPUs.
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*/
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int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_domain *d,
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u32 closid, enum resctrl_conf_type t, u32 cfg_val);
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u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_domain *d,
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u32 closid, enum resctrl_conf_type type);
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int resctrl_online_domain(struct rdt_resource *r, struct rdt_domain *d);
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void resctrl_offline_domain(struct rdt_resource *r, struct rdt_domain *d);
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/**
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* resctrl_arch_rmid_read() - Read the eventid counter corresponding to rmid
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* for this resource and domain.
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* @r: resource that the counter should be read from.
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* @d: domain that the counter should be read from.
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* @rmid: rmid of the counter to read.
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* @eventid: eventid to read, e.g. L3 occupancy.
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* @val: result of the counter read in bytes.
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*
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* Call from process context on a CPU that belongs to domain @d.
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*
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* Return:
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* 0 on success, or -EIO, -EINVAL etc on error.
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*/
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int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_domain *d,
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u32 rmid, enum resctrl_event_id eventid, u64 *val);
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/**
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* resctrl_arch_reset_rmid() - Reset any private state associated with rmid
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* and eventid.
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* @r: The domain's resource.
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* @d: The rmid's domain.
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* @rmid: The rmid whose counter values should be reset.
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* @eventid: The eventid whose counter values should be reset.
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*
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* This can be called from any CPU.
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*/
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void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_domain *d,
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u32 rmid, enum resctrl_event_id eventid);
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/**
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* resctrl_arch_reset_rmid_all() - Reset all private state associated with
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* all rmids and eventids.
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* @r: The resctrl resource.
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* @d: The domain for which all architectural counter state will
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* be cleared.
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*
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* This can be called from any CPU.
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*/
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void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_domain *d);
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extern unsigned int resctrl_rmid_realloc_threshold;
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extern unsigned int resctrl_rmid_realloc_limit;
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#endif /* _RESCTRL_H */
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