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Microchip LAN8740/LAN8742 PHYs support basic unicast, broadcast, and Magic Packet WoL. They have one pattern filter matching up to 128 bytes of frame data, which can be used to implement ARP or multicast WoL. ARP WoL matches any ARP frame with broadcast address. Multicast WoL matches any multicast frame. Signed-off-by: Tristram Ha <Tristram.Ha@microchip.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Link: https://lore.kernel.org/r/1690329270-2873-1-git-send-email-Tristram.Ha@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
75 lines
3.1 KiB
C
75 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_SMSCPHY_H__
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#define __LINUX_SMSCPHY_H__
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#define MII_LAN83C185_ISF 29 /* Interrupt Source Flags */
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#define MII_LAN83C185_IM 30 /* Interrupt Mask */
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#define MII_LAN83C185_CTRL_STATUS 17 /* Mode/Status Register */
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#define MII_LAN83C185_SPECIAL_MODES 18 /* Special Modes Register */
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#define MII_LAN83C185_ISF_INT1 (1<<1) /* Auto-Negotiation Page Received */
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#define MII_LAN83C185_ISF_INT2 (1<<2) /* Parallel Detection Fault */
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#define MII_LAN83C185_ISF_INT3 (1<<3) /* Auto-Negotiation LP Ack */
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#define MII_LAN83C185_ISF_INT4 (1<<4) /* Link Down */
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#define MII_LAN83C185_ISF_INT5 (1<<5) /* Remote Fault Detected */
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#define MII_LAN83C185_ISF_INT6 (1<<6) /* Auto-Negotiation complete */
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#define MII_LAN83C185_ISF_INT7 (1<<7) /* ENERGYON */
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#define MII_LAN83C185_ISF_INT_ALL (0x0e)
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#define MII_LAN83C185_ISF_INT_PHYLIB_EVENTS \
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(MII_LAN83C185_ISF_INT6 | MII_LAN83C185_ISF_INT4 | \
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MII_LAN83C185_ISF_INT7)
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#define MII_LAN83C185_EDPWRDOWN (1 << 13) /* EDPWRDOWN */
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#define MII_LAN83C185_ENERGYON (1 << 1) /* ENERGYON */
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#define MII_LAN83C185_MODE_MASK 0xE0
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#define MII_LAN83C185_MODE_POWERDOWN 0xC0 /* Power Down mode */
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#define MII_LAN83C185_MODE_ALL 0xE0 /* All capable mode */
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int smsc_phy_config_intr(struct phy_device *phydev);
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irqreturn_t smsc_phy_handle_interrupt(struct phy_device *phydev);
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int smsc_phy_config_init(struct phy_device *phydev);
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int lan87xx_read_status(struct phy_device *phydev);
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int smsc_phy_get_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, void *data);
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int smsc_phy_set_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, const void *data);
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int smsc_phy_probe(struct phy_device *phydev);
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#define MII_LAN874X_PHY_MMD_WOL_WUCSR 0x8010
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#define MII_LAN874X_PHY_MMD_WOL_WUF_CFGA 0x8011
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#define MII_LAN874X_PHY_MMD_WOL_WUF_CFGB 0x8012
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK0 0x8021
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK1 0x8022
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK2 0x8023
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK3 0x8024
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK4 0x8025
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK5 0x8026
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK6 0x8027
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#define MII_LAN874X_PHY_MMD_WOL_WUF_MASK7 0x8028
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#define MII_LAN874X_PHY_MMD_WOL_RX_ADDRA 0x8061
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#define MII_LAN874X_PHY_MMD_WOL_RX_ADDRB 0x8062
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#define MII_LAN874X_PHY_MMD_WOL_RX_ADDRC 0x8063
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#define MII_LAN874X_PHY_MMD_MCFGR 0x8064
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#define MII_LAN874X_PHY_PME1_SET (2 << 13)
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#define MII_LAN874X_PHY_PME2_SET (2 << 11)
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#define MII_LAN874X_PHY_PME_SELF_CLEAR BIT(9)
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#define MII_LAN874X_PHY_WOL_PFDA_FR BIT(7)
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#define MII_LAN874X_PHY_WOL_WUFR BIT(6)
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#define MII_LAN874X_PHY_WOL_MPR BIT(5)
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#define MII_LAN874X_PHY_WOL_BCAST_FR BIT(4)
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#define MII_LAN874X_PHY_WOL_PFDAEN BIT(3)
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#define MII_LAN874X_PHY_WOL_WUEN BIT(2)
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#define MII_LAN874X_PHY_WOL_MPEN BIT(1)
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#define MII_LAN874X_PHY_WOL_BCSTEN BIT(0)
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#define MII_LAN874X_PHY_WOL_FILTER_EN BIT(15)
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#define MII_LAN874X_PHY_WOL_FILTER_MCASTTEN BIT(9)
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#define MII_LAN874X_PHY_WOL_FILTER_BCSTEN BIT(8)
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#define MII_LAN874X_PHY_PME_SELF_CLEAR_DELAY 0x1000 /* 81 milliseconds */
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#endif /* __LINUX_SMSCPHY_H__ */
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