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![Kelvin Cao](/assets/img/avatar_default.png)
Advertise support of Gen5 devices in the driver's device ID table and add the same IDs for the switchtec quirks. Also update driver code to accommodate them. Link: https://lore.kernel.org/r/20230624000003.2315364-3-kelvin.cao@microchip.com Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
526 lines
11 KiB
C
526 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Microsemi Switchtec PCIe Driver
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* Copyright (c) 2017, Microsemi Corporation
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*/
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#ifndef _SWITCHTEC_H
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#define _SWITCHTEC_H
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#include <linux/pci.h>
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#include <linux/cdev.h>
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#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
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#define SWITCHTEC_MAX_PFF_CSR 255
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#define SWITCHTEC_EVENT_OCCURRED BIT(0)
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#define SWITCHTEC_EVENT_CLEAR BIT(0)
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#define SWITCHTEC_EVENT_EN_LOG BIT(1)
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#define SWITCHTEC_EVENT_EN_CLI BIT(2)
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#define SWITCHTEC_EVENT_EN_IRQ BIT(3)
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#define SWITCHTEC_EVENT_FATAL BIT(4)
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#define SWITCHTEC_EVENT_NOT_SUPP BIT(31)
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#define SWITCHTEC_DMA_MRPC_EN BIT(0)
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#define MRPC_GAS_READ 0x29
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#define MRPC_GAS_WRITE 0x87
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#define MRPC_CMD_ID(x) ((x) & 0xffff)
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enum {
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SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
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SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
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SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
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SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
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SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
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SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
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SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
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SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
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};
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enum switchtec_gen {
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SWITCHTEC_GEN3,
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SWITCHTEC_GEN4,
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SWITCHTEC_GEN5,
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};
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struct mrpc_regs {
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u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
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u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
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u32 cmd;
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u32 status;
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u32 ret_value;
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u32 dma_en;
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u64 dma_addr;
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u32 dma_vector;
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u32 dma_ver;
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} __packed;
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enum mrpc_status {
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SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
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SWITCHTEC_MRPC_STATUS_DONE = 2,
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SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
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SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
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};
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struct sw_event_regs {
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u64 event_report_ctrl;
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u64 reserved1;
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u64 part_event_bitmap;
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u64 reserved2;
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u32 global_summary;
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u32 reserved3[3];
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u32 stack_error_event_hdr;
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u32 stack_error_event_data;
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u32 reserved4[4];
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u32 ppu_error_event_hdr;
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u32 ppu_error_event_data;
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u32 reserved5[4];
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u32 isp_error_event_hdr;
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u32 isp_error_event_data;
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u32 reserved6[4];
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u32 sys_reset_event_hdr;
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u32 reserved7[5];
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u32 fw_exception_hdr;
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u32 reserved8[5];
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u32 fw_nmi_hdr;
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u32 reserved9[5];
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u32 fw_non_fatal_hdr;
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u32 reserved10[5];
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u32 fw_fatal_hdr;
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u32 reserved11[5];
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u32 twi_mrpc_comp_hdr;
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u32 twi_mrpc_comp_data;
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u32 reserved12[4];
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u32 twi_mrpc_comp_async_hdr;
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u32 twi_mrpc_comp_async_data;
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u32 reserved13[4];
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u32 cli_mrpc_comp_hdr;
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u32 cli_mrpc_comp_data;
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u32 reserved14[4];
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u32 cli_mrpc_comp_async_hdr;
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u32 cli_mrpc_comp_async_data;
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u32 reserved15[4];
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u32 gpio_interrupt_hdr;
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u32 gpio_interrupt_data;
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u32 reserved16[4];
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u32 gfms_event_hdr;
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u32 gfms_event_data;
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u32 reserved17[4];
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} __packed;
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enum {
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SWITCHTEC_GEN3_CFG0_RUNNING = 0x04,
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SWITCHTEC_GEN3_CFG1_RUNNING = 0x05,
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SWITCHTEC_GEN3_IMG0_RUNNING = 0x03,
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SWITCHTEC_GEN3_IMG1_RUNNING = 0x07,
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};
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enum {
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SWITCHTEC_GEN4_MAP0_RUNNING = 0x00,
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SWITCHTEC_GEN4_MAP1_RUNNING = 0x01,
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SWITCHTEC_GEN4_KEY0_RUNNING = 0x02,
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SWITCHTEC_GEN4_KEY1_RUNNING = 0x03,
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SWITCHTEC_GEN4_BL2_0_RUNNING = 0x04,
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SWITCHTEC_GEN4_BL2_1_RUNNING = 0x05,
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SWITCHTEC_GEN4_CFG0_RUNNING = 0x06,
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SWITCHTEC_GEN4_CFG1_RUNNING = 0x07,
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SWITCHTEC_GEN4_IMG0_RUNNING = 0x08,
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SWITCHTEC_GEN4_IMG1_RUNNING = 0x09,
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};
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enum {
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SWITCHTEC_GEN4_KEY0_ACTIVE = 0,
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SWITCHTEC_GEN4_KEY1_ACTIVE = 1,
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SWITCHTEC_GEN4_BL2_0_ACTIVE = 0,
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SWITCHTEC_GEN4_BL2_1_ACTIVE = 1,
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SWITCHTEC_GEN4_CFG0_ACTIVE = 0,
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SWITCHTEC_GEN4_CFG1_ACTIVE = 1,
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SWITCHTEC_GEN4_IMG0_ACTIVE = 0,
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SWITCHTEC_GEN4_IMG1_ACTIVE = 1,
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};
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struct sys_info_regs_gen3 {
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u32 reserved1;
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u32 vendor_table_revision;
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u32 table_format_version;
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u32 partition_id;
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u32 cfg_file_fmt_version;
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u16 cfg_running;
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u16 img_running;
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u32 reserved2[57];
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char vendor_id[8];
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char product_id[16];
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char product_revision[4];
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char component_vendor[8];
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u16 component_id;
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u8 component_revision;
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} __packed;
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struct sys_info_regs_gen4 {
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u16 gas_layout_ver;
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u8 evlist_ver;
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u8 reserved1;
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u16 mgmt_cmd_set_ver;
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u16 fabric_cmd_set_ver;
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u32 reserved2[2];
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u8 mrpc_uart_ver;
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u8 mrpc_twi_ver;
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u8 mrpc_eth_ver;
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u8 mrpc_inband_ver;
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u32 reserved3[7];
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u32 fw_update_tmo;
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u32 xml_version_cfg;
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u32 xml_version_img;
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u32 partition_id;
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u16 bl2_running;
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u16 cfg_running;
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u16 img_running;
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u16 key_running;
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u32 reserved4[43];
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u32 vendor_seeprom_twi;
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u32 vendor_table_revision;
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u32 vendor_specific_info[2];
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u16 p2p_vendor_id;
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u16 p2p_device_id;
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u8 p2p_revision_id;
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u8 reserved5[3];
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u32 p2p_class_id;
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u16 subsystem_vendor_id;
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u16 subsystem_id;
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u32 p2p_serial_number[2];
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u8 mac_addr[6];
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u8 reserved6[2];
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u32 reserved7[3];
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char vendor_id[8];
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char product_id[24];
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char product_revision[2];
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u16 reserved8;
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} __packed;
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struct sys_info_regs {
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u32 device_id;
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u32 device_version;
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u32 firmware_version;
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union {
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struct sys_info_regs_gen3 gen3;
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struct sys_info_regs_gen4 gen4;
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};
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} __packed;
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struct partition_info {
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u32 address;
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u32 length;
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};
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struct flash_info_regs_gen3 {
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u32 flash_part_map_upd_idx;
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struct active_partition_info_gen3 {
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u32 address;
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u32 build_version;
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u32 build_string;
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} active_img;
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struct active_partition_info_gen3 active_cfg;
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struct active_partition_info_gen3 inactive_img;
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struct active_partition_info_gen3 inactive_cfg;
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u32 flash_length;
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struct partition_info cfg0;
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struct partition_info cfg1;
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struct partition_info img0;
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struct partition_info img1;
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struct partition_info nvlog;
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struct partition_info vendor[8];
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};
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struct flash_info_regs_gen4 {
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u32 flash_address;
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u32 flash_length;
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struct active_partition_info_gen4 {
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unsigned char bl2;
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unsigned char cfg;
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unsigned char img;
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unsigned char key;
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} active_flag;
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u32 reserved[3];
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struct partition_info map0;
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struct partition_info map1;
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struct partition_info key0;
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struct partition_info key1;
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struct partition_info bl2_0;
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struct partition_info bl2_1;
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struct partition_info cfg0;
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struct partition_info cfg1;
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struct partition_info img0;
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struct partition_info img1;
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struct partition_info nvlog;
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struct partition_info vendor[8];
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};
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struct flash_info_regs {
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union {
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struct flash_info_regs_gen3 gen3;
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struct flash_info_regs_gen4 gen4;
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};
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};
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enum {
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SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
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SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
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SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
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};
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struct ntb_info_regs {
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u8 partition_count;
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u8 partition_id;
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u16 reserved1;
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u64 ep_map;
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u16 requester_id;
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u16 reserved2;
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u32 reserved3[4];
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struct nt_partition_info {
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u32 xlink_enabled;
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u32 target_part_low;
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u32 target_part_high;
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u32 reserved;
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} ntp_info[48];
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} __packed;
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struct part_cfg_regs {
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u32 status;
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u32 state;
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u32 port_cnt;
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u32 usp_port_mode;
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u32 usp_pff_inst_id;
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u32 vep_pff_inst_id;
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u32 dsp_pff_inst_id[47];
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u32 reserved1[11];
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u16 vep_vector_number;
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u16 usp_vector_number;
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u32 port_event_bitmap;
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u32 reserved2[3];
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u32 part_event_summary;
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u32 reserved3[3];
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u32 part_reset_hdr;
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u32 part_reset_data[5];
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u32 mrpc_comp_hdr;
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u32 mrpc_comp_data[5];
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u32 mrpc_comp_async_hdr;
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u32 mrpc_comp_async_data[5];
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u32 dyn_binding_hdr;
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u32 dyn_binding_data[5];
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u32 intercomm_notify_hdr;
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u32 intercomm_notify_data[5];
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u32 reserved4[153];
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} __packed;
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enum {
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NTB_CTRL_PART_OP_LOCK = 0x1,
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NTB_CTRL_PART_OP_CFG = 0x2,
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NTB_CTRL_PART_OP_RESET = 0x3,
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NTB_CTRL_PART_STATUS_NORMAL = 0x1,
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NTB_CTRL_PART_STATUS_LOCKED = 0x2,
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NTB_CTRL_PART_STATUS_LOCKING = 0x3,
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NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
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NTB_CTRL_PART_STATUS_RESETTING = 0x5,
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NTB_CTRL_BAR_VALID = 1 << 0,
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NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
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NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
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NTB_CTRL_REQ_ID_EN = 1 << 0,
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NTB_CTRL_LUT_EN = 1 << 0,
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};
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struct ntb_ctrl_regs {
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u32 partition_status;
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u32 partition_op;
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u32 partition_ctrl;
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u32 bar_setup;
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u32 bar_error;
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u16 lut_table_entries;
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u16 lut_table_offset;
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u32 lut_error;
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u16 req_id_table_size;
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u16 req_id_table_offset;
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u32 req_id_error;
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u32 reserved1[7];
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struct {
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u32 ctl;
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u32 win_size;
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u64 xlate_addr;
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} bar_entry[6];
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struct {
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u32 win_size;
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u32 reserved[3];
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} bar_ext_entry[6];
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u32 reserved2[192];
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u32 req_id_table[512];
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u32 reserved3[256];
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u64 lut_entry[512];
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} __packed;
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#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
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#define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
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struct ntb_dbmsg_regs {
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u32 reserved1[1024];
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u64 odb;
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u64 odb_mask;
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u64 idb;
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u64 idb_mask;
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u8 idb_vec_map[64];
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u32 msg_map;
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u32 reserved2;
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struct {
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u32 msg;
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u32 status;
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} omsg[4];
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struct {
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u32 msg;
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u8 status;
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u8 mask;
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u8 src;
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u8 reserved;
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} imsg[4];
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u8 reserved3[3928];
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u8 msix_table[1024];
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u8 reserved4[3072];
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u8 pba[24];
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u8 reserved5[4072];
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} __packed;
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enum {
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SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
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SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
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SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
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SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
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};
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struct pff_csr_regs {
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u16 vendor_id;
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u16 device_id;
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u16 pcicmd;
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u16 pcists;
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u32 pci_class;
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u32 pci_opts;
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union {
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u32 pci_bar[6];
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u64 pci_bar64[3];
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};
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u32 pci_cardbus;
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u32 pci_subsystem_id;
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u32 pci_expansion_rom;
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u32 pci_cap_ptr;
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u32 reserved1;
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u32 pci_irq;
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u32 pci_cap_region[48];
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u32 pcie_cap_region[448];
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u32 indirect_gas_window[128];
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u32 indirect_gas_window_off;
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u32 reserved[127];
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u32 pff_event_summary;
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u32 reserved2[3];
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u32 aer_in_p2p_hdr;
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u32 aer_in_p2p_data[5];
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u32 aer_in_vep_hdr;
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u32 aer_in_vep_data[5];
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u32 dpc_hdr;
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u32 dpc_data[5];
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u32 cts_hdr;
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u32 cts_data[5];
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u32 uec_hdr;
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u32 uec_data[5];
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u32 hotplug_hdr;
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u32 hotplug_data[5];
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u32 ier_hdr;
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u32 ier_data[5];
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u32 threshold_hdr;
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u32 threshold_data[5];
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u32 power_mgmt_hdr;
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u32 power_mgmt_data[5];
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u32 tlp_throttling_hdr;
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u32 tlp_throttling_data[5];
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u32 force_speed_hdr;
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u32 force_speed_data[5];
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u32 credit_timeout_hdr;
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u32 credit_timeout_data[5];
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u32 link_state_hdr;
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u32 link_state_data[5];
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u32 reserved4[174];
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} __packed;
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struct switchtec_ntb;
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struct dma_mrpc_output {
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u32 status;
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u32 cmd_id;
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u32 rtn_code;
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u32 output_size;
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u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
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};
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struct switchtec_dev {
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struct pci_dev *pdev;
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struct device dev;
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struct cdev cdev;
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enum switchtec_gen gen;
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int partition;
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int partition_count;
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int pff_csr_count;
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char pff_local[SWITCHTEC_MAX_PFF_CSR];
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void __iomem *mmio;
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struct mrpc_regs __iomem *mmio_mrpc;
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struct sw_event_regs __iomem *mmio_sw_event;
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struct sys_info_regs __iomem *mmio_sys_info;
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struct flash_info_regs __iomem *mmio_flash_info;
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struct ntb_info_regs __iomem *mmio_ntb;
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struct part_cfg_regs __iomem *mmio_part_cfg;
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struct part_cfg_regs __iomem *mmio_part_cfg_all;
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struct pff_csr_regs __iomem *mmio_pff_csr;
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/*
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* The mrpc mutex must be held when accessing the other
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* mrpc_ fields, alive flag and stuser->state field
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*/
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struct mutex mrpc_mutex;
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struct list_head mrpc_queue;
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int mrpc_busy;
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struct work_struct mrpc_work;
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struct delayed_work mrpc_timeout;
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bool alive;
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|
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wait_queue_head_t event_wq;
|
|
atomic_t event_cnt;
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|
|
|
struct work_struct link_event_work;
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void (*link_notifier)(struct switchtec_dev *stdev);
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u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
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|
|
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struct switchtec_ntb *sndev;
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|
|
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struct dma_mrpc_output *dma_mrpc;
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|
dma_addr_t dma_mrpc_dma_addr;
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|
};
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static inline struct switchtec_dev *to_stdev(struct device *dev)
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|
{
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return container_of(dev, struct switchtec_dev, dev);
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|
}
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|
|
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extern struct class *switchtec_class;
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|
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#endif
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