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856caabf72
The macros PERF_REGS_MAX and PERF_REGS_MASK are architecture specific, let's remove them from the common file util/perf_regs.c. As a side effect, the weak functions arch__intr_reg_mask() and arch__user_reg_mask() just return zeros, every arch defines its own functions in the 'arch' folder for returning right values. Note, we don't need to return intr/user register masks dynamically, this is because these two functions are invoked during recording phase but not decoding phase, they are always invoked on the native environment, thus we don't need to parse them dynamically. Signed-off-by: Leo Yan <leo.yan@linaro.org> Acked-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Eric Lin <eric.lin@sifive.com> Cc: Fangrui Song <maskray@google.com> Cc: Guo Ren <guoren@kernel.org> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ivan Babrou <ivan@cloudflare.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Ming Wang <wangming01@loongson.cn> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sandipan Das <sandipan.das@amd.com> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-csky@vger.kernel.org Cc: linux-riscv@lists.infradead.org Link: https://lore.kernel.org/r/20230606014559.21783-6-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
129 lines
3 KiB
C
129 lines
3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <errno.h>
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#include <string.h>
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#include "perf_regs.h"
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#include "util/sample.h"
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#include "debug.h"
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int __weak arch_sdt_arg_parse_op(char *old_op __maybe_unused,
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char **new_op __maybe_unused)
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{
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return SDT_ARG_SKIP;
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}
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uint64_t __weak arch__intr_reg_mask(void)
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{
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return 0;
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}
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uint64_t __weak arch__user_reg_mask(void)
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{
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return 0;
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}
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#ifdef HAVE_PERF_REGS_SUPPORT
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const char *perf_reg_name(int id, const char *arch)
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{
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const char *reg_name = NULL;
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if (!strcmp(arch, "csky"))
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reg_name = __perf_reg_name_csky(id);
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else if (!strcmp(arch, "loongarch"))
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reg_name = __perf_reg_name_loongarch(id);
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else if (!strcmp(arch, "mips"))
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reg_name = __perf_reg_name_mips(id);
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else if (!strcmp(arch, "powerpc"))
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reg_name = __perf_reg_name_powerpc(id);
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else if (!strcmp(arch, "riscv"))
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reg_name = __perf_reg_name_riscv(id);
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else if (!strcmp(arch, "s390"))
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reg_name = __perf_reg_name_s390(id);
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else if (!strcmp(arch, "x86"))
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reg_name = __perf_reg_name_x86(id);
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else if (!strcmp(arch, "arm"))
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reg_name = __perf_reg_name_arm(id);
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else if (!strcmp(arch, "arm64"))
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reg_name = __perf_reg_name_arm64(id);
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return reg_name ?: "unknown";
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}
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int perf_reg_value(u64 *valp, struct regs_dump *regs, int id)
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{
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int i, idx = 0;
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u64 mask = regs->mask;
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if ((u64)id >= PERF_SAMPLE_REGS_CACHE_SIZE)
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return -EINVAL;
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if (regs->cache_mask & (1ULL << id))
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goto out;
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if (!(mask & (1ULL << id)))
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return -EINVAL;
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for (i = 0; i < id; i++) {
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if (mask & (1ULL << i))
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idx++;
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}
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regs->cache_mask |= (1ULL << id);
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regs->cache_regs[id] = regs->regs[idx];
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out:
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*valp = regs->cache_regs[id];
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return 0;
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}
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uint64_t perf_arch_reg_ip(const char *arch)
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{
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if (!strcmp(arch, "arm"))
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return __perf_reg_ip_arm();
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else if (!strcmp(arch, "arm64"))
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return __perf_reg_ip_arm64();
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else if (!strcmp(arch, "csky"))
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return __perf_reg_ip_csky();
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else if (!strcmp(arch, "loongarch"))
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return __perf_reg_ip_loongarch();
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else if (!strcmp(arch, "mips"))
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return __perf_reg_ip_mips();
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else if (!strcmp(arch, "powerpc"))
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return __perf_reg_ip_powerpc();
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else if (!strcmp(arch, "riscv"))
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return __perf_reg_ip_riscv();
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else if (!strcmp(arch, "s390"))
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return __perf_reg_ip_s390();
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else if (!strcmp(arch, "x86"))
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return __perf_reg_ip_x86();
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pr_err("Fail to find IP register for arch %s, returns 0\n", arch);
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return 0;
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}
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uint64_t perf_arch_reg_sp(const char *arch)
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{
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if (!strcmp(arch, "arm"))
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return __perf_reg_sp_arm();
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else if (!strcmp(arch, "arm64"))
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return __perf_reg_sp_arm64();
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else if (!strcmp(arch, "csky"))
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return __perf_reg_sp_csky();
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else if (!strcmp(arch, "loongarch"))
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return __perf_reg_sp_loongarch();
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else if (!strcmp(arch, "mips"))
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return __perf_reg_sp_mips();
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else if (!strcmp(arch, "powerpc"))
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return __perf_reg_sp_powerpc();
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else if (!strcmp(arch, "riscv"))
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return __perf_reg_sp_riscv();
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else if (!strcmp(arch, "s390"))
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return __perf_reg_sp_s390();
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else if (!strcmp(arch, "x86"))
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return __perf_reg_sp_x86();
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pr_err("Fail to find SP register for arch %s, returns 0\n", arch);
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return 0;
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}
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#endif
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