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a3c4946db4
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
289 lines
5.9 KiB
C
289 lines
5.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
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* Copyright (C) MIPS Technologies, Inc.
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef _ASM_HAZARDS_H
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#define _ASM_HAZARDS_H
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#include <linux/config.h>
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#ifdef __ASSEMBLY__
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.macro _ssnop
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sll $0, $0, 1
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.endm
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.macro _ehb
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sll $0, $0, 3
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.endm
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/*
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* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
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* use of the JTLB for instructions should not occur for 4 cpu cycles and use
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* for data translations should not occur for 3 cpu cycles.
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*/
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#ifdef CONFIG_CPU_RM9000
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.macro mtc0_tlbw_hazard
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.set push
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.set mips32
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_ssnop; _ssnop; _ssnop; _ssnop
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.set pop
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.endm
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.macro tlbw_eret_hazard
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.set push
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.set mips32
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_ssnop; _ssnop; _ssnop; _ssnop
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.set pop
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.endm
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#else
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/*
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* The taken branch will result in a two cycle penalty for the two killed
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* instructions on R4000 / R4400. Other processors only have a single cycle
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* hazard so this is nice trick to have an optimal code for a range of
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* processors.
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*/
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.macro mtc0_tlbw_hazard
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b . + 8
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.endm
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.macro tlbw_eret_hazard
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.endm
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#endif
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/*
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* mtc0->mfc0 hazard
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* The 24K has a 2 cycle mtc0/mfc0 execution hazard.
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* It is a MIPS32R2 processor so ehb will clear the hazard.
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*/
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#ifdef CONFIG_CPU_MIPSR2
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/*
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* Use a macro for ehb unless explicit support for MIPSR2 is enabled
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*/
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#define irq_enable_hazard
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_ehb
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#define irq_disable_hazard
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_ehb
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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*/
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#define irq_enable_hazard
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#define irq_disable_hazard
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#else
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/*
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* Classic MIPS needs 1 - 3 nops or ssnops
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*/
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#define irq_enable_hazard
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#define irq_disable_hazard \
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_ssnop; _ssnop; _ssnop
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#endif
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#else /* __ASSEMBLY__ */
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__asm__(
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" .macro _ssnop \n"
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" sll $0, $0, 1 \n"
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" .endm \n"
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" \n"
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" .macro _ehb \n"
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" sll $0, $0, 3 \n"
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" .endm \n");
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#ifdef CONFIG_CPU_RM9000
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/*
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* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
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* use of the JTLB for instructions should not occur for 4 cpu cycles and use
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* for data translations should not occur for 3 cpu cycles.
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*/
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#define mtc0_tlbw_hazard() \
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__asm__ __volatile__( \
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" .set mips32 \n" \
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" _ssnop \n" \
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" _ssnop \n" \
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" _ssnop \n" \
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" _ssnop \n" \
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" .set mips0 \n")
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#define tlbw_use_hazard() \
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__asm__ __volatile__( \
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" .set mips32 \n" \
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" _ssnop \n" \
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" _ssnop \n" \
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" _ssnop \n" \
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" _ssnop \n" \
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" .set mips0 \n")
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#else
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/*
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* Overkill warning ...
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*/
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#define mtc0_tlbw_hazard() \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" .set reorder \n")
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#define tlbw_use_hazard() \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" nop \n" \
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" .set reorder \n")
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#endif
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/*
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* Interrupt enable/disable hazards
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* Some processors have hazards when modifying
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* the status register to change the interrupt state
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*/
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#ifdef CONFIG_CPU_MIPSR2
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__asm__(" .macro irq_enable_hazard \n"
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" _ehb \n"
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" .endm \n"
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" \n"
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" .macro irq_disable_hazard \n"
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" _ehb \n"
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" .endm \n");
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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*/
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__asm__(
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" .macro irq_enable_hazard \n"
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" .endm \n"
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" \n"
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" .macro irq_disable_hazard \n"
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" .endm \n");
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#else
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/*
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* Default for classic MIPS processors. Assume worst case hazards but don't
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* care about the irq_enable_hazard - sooner or later the hardware will
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* enable it and we don't care when exactly.
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*/
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__asm__(
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" # \n"
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" # There is a hazard but we do not care \n"
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" # \n"
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" .macro\tirq_enable_hazard \n"
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" .endm \n"
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" \n"
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" .macro\tirq_disable_hazard \n"
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" _ssnop \n"
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" _ssnop \n"
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" _ssnop \n"
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" .endm \n");
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#endif
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#define irq_enable_hazard() \
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__asm__ __volatile__("irq_enable_hazard")
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#define irq_disable_hazard() \
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__asm__ __volatile__("irq_disable_hazard")
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/*
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* Back-to-back hazards -
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*
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* What is needed to separate a move to cp0 from a subsequent read from the
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* same cp0 register?
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*/
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#ifdef CONFIG_CPU_MIPSR2
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__asm__(" .macro back_to_back_c0_hazard \n"
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" _ehb \n"
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" .endm \n");
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#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
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defined(CONFIG_CPU_SB1)
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__asm__(" .macro back_to_back_c0_hazard \n"
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" .endm \n");
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#else
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__asm__(" .macro back_to_back_c0_hazard \n"
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" .set noreorder \n"
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" _ssnop \n"
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" _ssnop \n"
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" _ssnop \n"
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" .set reorder \n"
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" .endm");
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#endif
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#define back_to_back_c0_hazard() \
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__asm__ __volatile__("back_to_back_c0_hazard")
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/*
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* Instruction execution hazard
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*/
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#ifdef CONFIG_CPU_MIPSR2
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/*
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* gcc has a tradition of misscompiling the previous construct using the
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* address of a label as argument to inline assembler. Gas otoh has the
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* annoying difference between la and dla which are only usable for 32-bit
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* rsp. 64-bit code, so can't be used without conditional compilation.
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* The alterantive is switching the assembler to 64-bit code which happens
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* to work right even for 32-bit code ...
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*/
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#define instruction_hazard() \
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do { \
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unsigned long tmp; \
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\
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__asm__ __volatile__( \
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" .set mips64r2 \n" \
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" dla %0, 1f \n" \
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" jr.hb %0 \n" \
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" .set mips0 \n" \
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"1: \n" \
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: "=r" (tmp)); \
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} while (0)
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#else
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#define instruction_hazard() do { } while (0)
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_HAZARDS_H */
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