mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-11-01 17:08:10 +00:00
58390c8ce1
Including:
- Convert to platform remove callback returning void
- Extend changing default domain to normal group
- Intel VT-d updates:
- Remove VT-d virtual command interface and IOASID
- Allow the VT-d driver to support non-PRI IOPF
- Remove PASID supervisor request support
- Various small and misc cleanups
- ARM SMMU updates:
- Device-tree binding updates:
* Allow Qualcomm GPU SMMUs to accept relevant clock properties
* Document Qualcomm 8550 SoC as implementing an MMU-500
* Favour new "qcom,smmu-500" binding for Adreno SMMUs
- Fix S2CR quirk detection on non-architectural Qualcomm SMMU
implementations
- Acknowledge SMMUv3 PRI queue overflow when consuming events
- Document (in a comment) why ATS is disabled for bypass streams
- AMD IOMMU updates:
- 5-level page-table support
- NUMA awareness for memory allocations
- Unisoc driver: Support for reattaching an existing domain
- Rockchip driver: Add missing set_platform_dma_ops callback
- Mediatek driver: Adjust the dma-ranges
- Various other small fixes and cleanups
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Merge tag 'iommu-updates-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel:
- Convert to platform remove callback returning void
- Extend changing default domain to normal group
- Intel VT-d updates:
- Remove VT-d virtual command interface and IOASID
- Allow the VT-d driver to support non-PRI IOPF
- Remove PASID supervisor request support
- Various small and misc cleanups
- ARM SMMU updates:
- Device-tree binding updates:
* Allow Qualcomm GPU SMMUs to accept relevant clock properties
* Document Qualcomm 8550 SoC as implementing an MMU-500
* Favour new "qcom,smmu-500" binding for Adreno SMMUs
- Fix S2CR quirk detection on non-architectural Qualcomm SMMU
implementations
- Acknowledge SMMUv3 PRI queue overflow when consuming events
- Document (in a comment) why ATS is disabled for bypass streams
- AMD IOMMU updates:
- 5-level page-table support
- NUMA awareness for memory allocations
- Unisoc driver: Support for reattaching an existing domain
- Rockchip driver: Add missing set_platform_dma_ops callback
- Mediatek driver: Adjust the dma-ranges
- Various other small fixes and cleanups
* tag 'iommu-updates-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (82 commits)
iommu: Remove iommu_group_get_by_id()
iommu: Make iommu_release_device() static
iommu/vt-d: Remove BUG_ON in dmar_insert_dev_scope()
iommu/vt-d: Remove a useless BUG_ON(dev->is_virtfn)
iommu/vt-d: Remove BUG_ON in map/unmap()
iommu/vt-d: Remove BUG_ON when domain->pgd is NULL
iommu/vt-d: Remove BUG_ON in handling iotlb cache invalidation
iommu/vt-d: Remove BUG_ON on checking valid pfn range
iommu/vt-d: Make size of operands same in bitwise operations
iommu/vt-d: Remove PASID supervisor request support
iommu/vt-d: Use non-privileged mode for all PASIDs
iommu/vt-d: Remove extern from function prototypes
iommu/vt-d: Do not use GFP_ATOMIC when not needed
iommu/vt-d: Remove unnecessary checks in iopf disabling path
iommu/vt-d: Move PRI handling to IOPF feature path
iommu/vt-d: Move pfsid and ats_qdep calculation to device probe path
iommu/vt-d: Move iopf code from SVA to IOPF enabling path
iommu/vt-d: Allow SVA with device-specific IOPF
dmaengine: idxd: Add enable/disable device IOPF feature
arm64: dts: mt8186: Add dma-ranges for the parent "soc" node
...
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/mm_types.h>
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#include <linux/maple_tree.h>
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#include <linux/rwsem.h>
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#include <linux/spinlock.h>
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#include <linux/list.h>
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#include <linux/cpumask.h>
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#include <linux/mman.h>
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#include <linux/pgtable.h>
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#include <linux/atomic.h>
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#include <linux/user_namespace.h>
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#include <linux/iommu.h>
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#include <asm/mmu.h>
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#ifndef INIT_MM_CONTEXT
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#define INIT_MM_CONTEXT(name)
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#endif
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/*
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* For dynamically allocated mm_structs, there is a dynamically sized cpumask
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* at the end of the structure, the size of which depends on the maximum CPU
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* number the system can see. That way we allocate only as much memory for
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* mm_cpumask() as needed for the hundreds, or thousands of processes that
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* a system typically runs.
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*
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* Since there is only one init_mm in the entire system, keep it simple
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* and size this cpu_bitmask to NR_CPUS.
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*/
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struct mm_struct init_mm = {
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.mm_mt = MTREE_INIT_EXT(mm_mt, MM_MT_FLAGS, init_mm.mmap_lock),
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.pgd = swapper_pg_dir,
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.mm_users = ATOMIC_INIT(2),
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.mm_count = ATOMIC_INIT(1),
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.write_protect_seq = SEQCNT_ZERO(init_mm.write_protect_seq),
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MMAP_LOCK_INITIALIZER(init_mm)
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.page_table_lock = __SPIN_LOCK_UNLOCKED(init_mm.page_table_lock),
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.arg_lock = __SPIN_LOCK_UNLOCKED(init_mm.arg_lock),
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.mmlist = LIST_HEAD_INIT(init_mm.mmlist),
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#ifdef CONFIG_PER_VMA_LOCK
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.mm_lock_seq = 0,
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#endif
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.user_ns = &init_user_ns,
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.cpu_bitmap = CPU_BITS_NONE,
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#ifdef CONFIG_IOMMU_SVA
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.pasid = IOMMU_PASID_INVALID,
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#endif
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INIT_MM_CONTEXT(init_mm)
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};
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void setup_initial_init_mm(void *start_code, void *end_code,
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void *end_data, void *brk)
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{
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init_mm.start_code = (unsigned long)start_code;
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init_mm.end_code = (unsigned long)end_code;
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init_mm.end_data = (unsigned long)end_data;
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init_mm.brk = (unsigned long)brk;
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}
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