linux-stable/drivers/clk/tegra
Linus Torvalds 75d6e7d9ce Nothing changed in the clk framework core this time around. We did get
some updates to the basic clk types to use determine_rate for the
 divider type and add a power of two fractional divider flag though.
 Otherwise, this is a collection of clk driver updates. More than half
 the diffstat is in the Qualcomm clk driver where we add a bunch of data
 to describe clks on various SoCs and fix bugs. The other big new thing
 in here is the Mediatek MT8192 clk driver. That's been under review for
 a while and it's nice to see that it's finally upstream.
 
 Beyond that it's the usual set of minor fixes and tweaks to clk drivers.
 There are some non-clk driver bits in here which have all been acked by
 the respective maintainers.
 
 New Drivers:
  - Support video, gpu, display clks on qcom sc7280 SoCs
  - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
  - Multimedia clks (MMCC) on qcom MSM8994/MSM8992
  - RPMh clks on qcom SM6350 SoCs
  - Support for Mediatek MT8192 SoCs
  - Add display (DU and DSI) clocks on Renesas R-Car V3U
  - Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and
    resets on Renesas RZ/G2L
 
 Updates:
  - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators
  - Add power of two flag to fractional divider clk type
  - Migrate some clk drivers to clk_divider_ops.determine_rate
  - Migrate to clk_parent_data in gcc-sdm660
  - Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2
  - Switch from .round_rate to .determine_rate in clk-divider-gate
  - Fix clock tree update for TF-A controlled clocks for all i.MX8M
  - Add missing M7 core clock for i.MX8MN
  - YAML conversion of rk3399 clock controller binding
  - Removal of GRF dependency for the rk3328/rk3036 pll types
  - Drop CLK_IS_CRITICAL flag from Tegra fuse clk
  - Make CLK_R9A06G032 Kconfig symbol invisible
  - Convert various DT bindings to YAML
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmExEooRHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSXXBhAAvhHm4fcm3fRjNdfImd+jDEl8XSvg+w43
 adSnmVxbYM6ZVNOiJ4CJWHbj0hOY/PJnsQYWbV0xXvXW+zXva6p495MMHHOGSi2o
 lMgZVMvj5UAwu304ZC9Xfn31dwo8XdGrltp4JqIcI2NEBMh1/PlZW22esT+jDiWN
 3SWFD3M7lu88xTREyiEu11FY3z/KiGzbGlqYcbivx1X0sHVnBRbl4qcqZway+BmQ
 95Ma4YWwhvDGYc+ypKH2EPxs/LikHXj05nMooigy65DOQ5wrM4L1eWkwmVUf6h+e
 t4x7sAVysLnkihzdH5r2pw6CcAIom76v8w0+maSfk+jINUu1LeGVuat1eXSesFTu
 49o+uTKRghkUe/Qh6r+7lbo8AZXQq+wUsLTYRuaWT/mSb+svAtJaUWAru8tJnMlH
 oK6OehcQwz4nGhH0HnBK1jCVdtgckxPBw8F/GYN9rYhsccIe0XmFjX1rzMM3s8De
 PLl6QO7Xzd+xb/FwAU8+S1WpKFdPU6ILTUnI2Ma3Mn/gfjZEZHvWAdTjo4oZGEsw
 +N4n924ArptbeSLRrlNUtqx4BVDL5yo54xS5gefNpmD5yezO7aoUtN0aGcBq+01p
 Qw0N5hKtcdsNYLBEFSvBGcZZmErMZbPwMXHWiUwNymXBDzJKgj5d+ks+1vJ3iCNW
 R5r9hvATJPQ=
 =Rrqg
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Nothing changed in the clk framework core this time around. We did get
  some updates to the basic clk types to use determine_rate for the
  divider type and add a power of two fractional divider flag though.

  Otherwise, this is a collection of clk driver updates. More than half
  the diffstat is in the Qualcomm clk driver where we add a bunch of
  data to describe clks on various SoCs and fix bugs. The other big new
  thing in here is the Mediatek MT8192 clk driver. That's been under
  review for a while and it's nice to see that it's finally upstream.

  Beyond that it's the usual set of minor fixes and tweaks to clk
  drivers. There are some non-clk driver bits in here which have all
  been acked by the respective maintainers.

  New Drivers:
   - Support video, gpu, display clks on qcom sc7280 SoCs
   - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
   - Multimedia clks (MMCC) on qcom MSM8994/MSM8992
   - RPMh clks on qcom SM6350 SoCs
   - Support for Mediatek MT8192 SoCs
   - Add display (DU and DSI) clocks on Renesas R-Car V3U
   - Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and
     resets on Renesas RZ/G2L

  Updates:
   - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators
   - Add power of two flag to fractional divider clk type
   - Migrate some clk drivers to clk_divider_ops.determine_rate
   - Migrate to clk_parent_data in gcc-sdm660
   - Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2
   - Switch from .round_rate to .determine_rate in clk-divider-gate
   - Fix clock tree update for TF-A controlled clocks for all i.MX8M
   - Add missing M7 core clock for i.MX8MN
   - YAML conversion of rk3399 clock controller binding
   - Removal of GRF dependency for the rk3328/rk3036 pll types
   - Drop CLK_IS_CRITICAL flag from Tegra fuse clk
   - Make CLK_R9A06G032 Kconfig symbol invisible
   - Convert various DT bindings to YAML"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits)
  dt-bindings: clock: samsung: fix header path in example
  clk: tegra: fix old-style declaration
  clk: qcom: Add SM6350 GCC driver
  MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
  dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos4 to dtschema
  dt-bindings: clock: samsung: convert Exynos3250 to dtschema
  dt-bindings: clock: samsung: convert Exynos542x to dtschema
  dt-bindings: clock: samsung: add bindings for Exynos external clock
  dt-bindings: clock: samsung: convert Exynos5250 to dtschema
  clk: vc5: Add properties for configuring SD/OE behavior
  clk: vc5: Use dev_err_probe
  dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
  dt-bindings: clock: brcm,iproc-clocks: fix armpll properties
  clk: zynqmp: Fix kernel-doc format
  clk: at91: clk-generated: Limit the requested rate to our range
  clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates
  clk: zynqmp: Fix a memory leak
  clk: zynqmp: Check the return type
  ...
2021-09-02 14:17:24 -07:00
..
clk-audio-sync.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 2019-05-30 11:29:52 -07:00
clk-bpmp.c clk: tegra: bpmp: Clamp clock rates on requests 2020-11-26 16:28:07 +01:00
clk-dfll.c clk: tegra: fix old-style declaration 2021-08-29 11:38:11 -07:00
clk-dfll.h clk: tegra: clk-dfll: Add suspend and resume support 2019-11-11 14:53:03 +01:00
clk-divider.c clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation 2020-01-10 15:50:05 +01:00
clk-id.h clk: tegra: Fix duplicated SE clock entry 2020-12-10 12:51:59 -08:00
clk-periph-fixed.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 2019-05-30 11:29:52 -07:00
clk-periph-gate.c clk: tegra: Don't deassert reset on enabling clocks 2021-05-31 15:16:46 +02:00
clk-periph.c clk: tegra: Fix refcounting of gate clocks 2021-05-31 15:16:24 +02:00
clk-pll-out.c clk: tegra: pllout: Save and restore pllout context 2019-11-11 14:53:02 +01:00
clk-pll.c clk: tegra: Don't allow zero clock rate for PLLs 2021-05-31 15:16:26 +02:00
clk-sdmmc-mux.c clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops 2021-07-27 14:54:19 -07:00
clk-super.c clk: tegra: clk-super: Add restore-context support 2019-11-11 14:53:03 +01:00
clk-tegra-audio.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 2019-05-30 11:29:52 -07:00
clk-tegra-fixed.c clk: tegra: Remove CLK_M_DIV fixed clocks 2020-03-12 11:33:32 +01:00
clk-tegra-periph.c clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock 2021-08-11 11:57:01 +02:00
clk-tegra-super-cclk.c clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling 2021-05-31 15:16:26 +02:00
clk-tegra-super-gen4.c clk: tegra: clk-super: Fix to enable PLLP branches to CPU 2019-11-11 14:53:03 +01:00
clk-tegra20-emc.c clk: tegra: Export Tegra20 EMC kernel symbols 2020-11-06 19:24:04 +01:00
clk-tegra20.c clk: tegra: Halve SCLK rate on Tegra20 2021-05-31 15:16:25 +02:00
clk-tegra30.c clk: tegra: Don't deassert reset on enabling clocks 2021-05-31 15:16:46 +02:00
clk-tegra114.c clk: tegra: Remove audio clocks configuration from clock driver 2020-03-12 12:10:49 +01:00
clk-tegra124-dfll-fcpu.c clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulator 2021-06-25 16:23:07 -07:00
clk-tegra124-emc.c clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing() 2021-06-02 11:08:00 +02:00
clk-tegra124.c memory: tegra124-emc: Make driver modular 2021-01-05 18:00:09 +01:00
clk-tegra210-emc.c This pull request contains zero diff to the core framework. It is a collection 2020-10-22 12:53:28 -07:00
clk-tegra210.c clk: tegra: Add PLLE HW power sequencer control 2021-03-24 14:01:58 +01:00
clk-utils.c clk: tegra: Refactor fractional divider calculation 2018-07-25 13:43:34 -07:00
clk.c clk: tegra: Fix double-free in tegra_clk_init() 2019-12-24 00:01:06 -08:00
clk.h clk: tegra: Don't deassert reset on enabling clocks 2021-05-31 15:16:46 +02:00
cvb.c clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s align param 2021-02-11 11:56:05 -08:00
cvb.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 2019-05-30 11:26:41 -07:00
Kconfig memory: tegra124-emc: Make driver modular 2021-01-05 18:00:09 +01:00
Makefile memory: tegra124-emc: Make driver modular 2021-01-05 18:00:09 +01:00