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9cc2a68519
The clock control module (CRM) cannot always provide desired frequency for all VOU output devices. That's why VOU integrates a few dividers to further divide the clocks from CRM. Let's add an interface for configuring these dividers. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Sean Paul <seanpaul@chromium.org>
70 lines
1.5 KiB
C
70 lines
1.5 KiB
C
/*
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* Copyright 2016 Linaro Ltd.
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* Copyright 2016 ZTE Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ZX_VOU_H__
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#define __ZX_VOU_H__
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#define VOU_CRTC_MASK 0x3
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/* VOU output interfaces */
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enum vou_inf_id {
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VOU_HDMI = 0,
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VOU_RGB_LCD = 1,
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VOU_TV_ENC = 2,
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VOU_MIPI_DSI = 3,
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VOU_LVDS = 4,
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VOU_VGA = 5,
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};
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enum vou_inf_hdmi_audio {
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VOU_HDMI_AUD_SPDIF = BIT(0),
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VOU_HDMI_AUD_I2S = BIT(1),
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VOU_HDMI_AUD_DSD = BIT(2),
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VOU_HDMI_AUD_HBR = BIT(3),
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VOU_HDMI_AUD_PARALLEL = BIT(4),
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};
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void vou_inf_hdmi_audio_sel(struct drm_crtc *crtc,
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enum vou_inf_hdmi_audio aud);
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void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc);
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void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc);
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enum vou_div_id {
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VOU_DIV_VGA,
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VOU_DIV_PIC,
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VOU_DIV_TVENC,
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VOU_DIV_HDMI_PNX,
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VOU_DIV_HDMI,
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VOU_DIV_INF,
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VOU_DIV_LAYER,
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};
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enum vou_div_val {
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VOU_DIV_1 = 0,
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VOU_DIV_2 = 1,
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VOU_DIV_4 = 3,
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VOU_DIV_8 = 7,
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};
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struct vou_div_config {
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enum vou_div_id id;
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enum vou_div_val val;
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};
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void zx_vou_config_dividers(struct drm_crtc *crtc,
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struct vou_div_config *configs, int num);
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int zx_vou_enable_vblank(struct drm_device *drm, unsigned int pipe);
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void zx_vou_disable_vblank(struct drm_device *drm, unsigned int pipe);
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void zx_vou_layer_enable(struct drm_plane *plane);
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void zx_vou_layer_disable(struct drm_plane *plane);
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#endif /* __ZX_VOU_H__ */
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