mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-26 20:38:12 +00:00
31ab516980
The RTC section of the H616 manual mentions in a half-sentence the existence of a clock "32K divided by PLL_PERI(2X)". This is used as one of the possible inputs for the mux that selects the clock for the 32 KHz fanout pad. On the H616 this is routed to pin PG10, and some boards use that clock output to compensate for a missing 32KHz crystal. On the OrangePi Zero2 this is for instance connected to the LPO pin of the WiFi/BT chip. The new RTC clock binding requires this clock to be named as one input clock, so we need to expose this to the DT. In contrast to the D1 SoC there does not seem to be a gate for this clock, so just use a fixed divider clock, using a newly assigned clock number. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220428230933.15262-3-andre.przywara@arm.com
56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright 2020 Arm Ltd.
|
|
*/
|
|
|
|
#ifndef _CCU_SUN50I_H616_H_
|
|
#define _CCU_SUN50I_H616_H_
|
|
|
|
#include <dt-bindings/clock/sun50i-h616-ccu.h>
|
|
#include <dt-bindings/reset/sun50i-h616-ccu.h>
|
|
|
|
#define CLK_OSC12M 0
|
|
#define CLK_PLL_CPUX 1
|
|
#define CLK_PLL_DDR0 2
|
|
#define CLK_PLL_DDR1 3
|
|
|
|
/* PLL_PERIPH0 exported for PRCM */
|
|
|
|
#define CLK_PLL_PERIPH0_2X 5
|
|
#define CLK_PLL_PERIPH1 6
|
|
#define CLK_PLL_PERIPH1_2X 7
|
|
#define CLK_PLL_GPU 8
|
|
#define CLK_PLL_VIDEO0 9
|
|
#define CLK_PLL_VIDEO0_4X 10
|
|
#define CLK_PLL_VIDEO1 11
|
|
#define CLK_PLL_VIDEO1_4X 12
|
|
#define CLK_PLL_VIDEO2 13
|
|
#define CLK_PLL_VIDEO2_4X 14
|
|
#define CLK_PLL_VE 15
|
|
#define CLK_PLL_DE 16
|
|
#define CLK_PLL_AUDIO_HS 17
|
|
#define CLK_PLL_AUDIO_1X 18
|
|
#define CLK_PLL_AUDIO_2X 19
|
|
#define CLK_PLL_AUDIO_4X 20
|
|
|
|
/* CPUX clock exported for DVFS */
|
|
|
|
#define CLK_AXI 22
|
|
#define CLK_CPUX_APB 23
|
|
#define CLK_PSI_AHB1_AHB2 24
|
|
#define CLK_AHB3 25
|
|
|
|
/* APB1 clock exported for PIO */
|
|
|
|
#define CLK_APB2 27
|
|
#define CLK_MBUS 28
|
|
|
|
/* All module clocks and bus gates are exported except DRAM */
|
|
|
|
#define CLK_DRAM 49
|
|
|
|
#define CLK_BUS_DRAM 56
|
|
|
|
#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1)
|
|
|
|
#endif /* _CCU_SUN50I_H616_H_ */
|