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6b457d31ea
This patch just implements the basic enable and disable functions of DC5 state which is needed for both SKL and BXT. Its important to load respective CSR program before calling enable, which anyways will happen as CSR program is executed during boot. DC5 is a power saving state where hardware dynamically disables power well 1 and the CDCLK PLL and saves the associated registers. DC5 can be entered when software allows it, power well 2 is disabled, and hardware detects that all pipes are disabled or pipe A is enabled with PSR active. Its better to configure display engine to have power well 2 disabled before getting into DC5 enable function. Hence rpm framework will have to ensure to check status of power well 2 before calling gen9_enable_dc5. Rather dc5 entry criteria should be decided based on power well 2 status. If disabled, then call gen9_enable_dc5. v2: Replace HAS_ with IS_ check as per Daniel's review comments v3: Cleared the bits dc5/dc6 enable of DC_STATE_EN register before setting them as per Satheesh's review comments. v4: call POSTING_READ for every write to a register to ensure that its written immediately. v5: Modified as per review comments from Imre. - Squashed register definitions into this patch. - Finetuned comments and functions. v6: Avoid redundant writes in gen9_set_dc_state_debugmask_memory_up function. v7: - Rebase to latest. - Move all runtime PM functions defined in intel_display.c to intel_runtime_pm.c. v8: Rebased to drm-intel-nightly. (Animesh) Issue: VIZ-2819 Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
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| .. | ||
| dvo.h | ||
| dvo_ch7xxx.c | ||
| dvo_ch7017.c | ||
| dvo_ivch.c | ||
| dvo_ns2501.c | ||
| dvo_sil164.c | ||
| dvo_tfp410.c | ||
| i915_cmd_parser.c | ||
| i915_debugfs.c | ||
| i915_dma.c | ||
| i915_drv.c | ||
| i915_drv.h | ||
| i915_gem.c | ||
| i915_gem_batch_pool.c | ||
| i915_gem_batch_pool.h | ||
| i915_gem_context.c | ||
| i915_gem_debug.c | ||
| i915_gem_dmabuf.c | ||
| i915_gem_evict.c | ||
| i915_gem_execbuffer.c | ||
| i915_gem_gtt.c | ||
| i915_gem_gtt.h | ||
| i915_gem_render_state.c | ||
| i915_gem_render_state.h | ||
| i915_gem_shrinker.c | ||
| i915_gem_stolen.c | ||
| i915_gem_tiling.c | ||
| i915_gem_userptr.c | ||
| i915_gpu_error.c | ||
| i915_ioc32.c | ||
| i915_irq.c | ||
| i915_params.c | ||
| i915_reg.h | ||
| i915_suspend.c | ||
| i915_sysfs.c | ||
| i915_trace.h | ||
| i915_trace_points.c | ||
| i915_vgpu.c | ||
| i915_vgpu.h | ||
| intel_acpi.c | ||
| intel_atomic.c | ||
| intel_atomic_plane.c | ||
| intel_audio.c | ||
| intel_bios.c | ||
| intel_bios.h | ||
| intel_crt.c | ||
| intel_csr.c | ||
| intel_ddi.c | ||
| intel_display.c | ||
| intel_dp.c | ||
| intel_dp_mst.c | ||
| intel_drv.h | ||
| intel_dsi.c | ||
| intel_dsi.h | ||
| intel_dsi_panel_vbt.c | ||
| intel_dsi_pll.c | ||
| intel_dvo.c | ||
| intel_fbc.c | ||
| intel_fbdev.c | ||
| intel_fifo_underrun.c | ||
| intel_frontbuffer.c | ||
| intel_hdmi.c | ||
| intel_i2c.c | ||
| intel_lrc.c | ||
| intel_lrc.h | ||
| intel_lvds.c | ||
| intel_modes.c | ||
| intel_opregion.c | ||
| intel_overlay.c | ||
| intel_panel.c | ||
| intel_pm.c | ||
| intel_psr.c | ||
| intel_renderstate.h | ||
| intel_renderstate_gen6.c | ||
| intel_renderstate_gen7.c | ||
| intel_renderstate_gen8.c | ||
| intel_renderstate_gen9.c | ||
| intel_ringbuffer.c | ||
| intel_ringbuffer.h | ||
| intel_runtime_pm.c | ||
| intel_sdvo.c | ||
| intel_sdvo_regs.h | ||
| intel_sideband.c | ||
| intel_sprite.c | ||
| intel_tv.c | ||
| intel_uncore.c | ||
| Kconfig | ||
| Makefile | ||