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![Xiantao Zhang](/assets/img/avatar_default.png)
Since vmm runs in an isolated address space and it is just a copy of host's kvm-intel module, so once vmm crashes, we just crash all guests running on it instead of crashing whole kernel. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by: Avi Kivity <avi@redhat.com>
748 lines
20 KiB
C
748 lines
20 KiB
C
/*
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* vcpu.h: vcpu routines
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* Copyright (c) 2005, Intel Corporation.
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* Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
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* Yaozu Dong (Eddie Dong) (Eddie.dong@intel.com)
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*
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* Copyright (c) 2007, Intel Corporation.
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* Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
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* Xiantao Zhang (xiantao.zhang@intel.com)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#ifndef __KVM_VCPU_H__
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#define __KVM_VCPU_H__
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#include <asm/types.h>
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#include <asm/fpu.h>
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#include <asm/processor.h>
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#ifndef __ASSEMBLY__
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#include "vti.h"
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#include <linux/kvm_host.h>
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#include <linux/spinlock.h>
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typedef unsigned long IA64_INST;
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typedef union U_IA64_BUNDLE {
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unsigned long i64[2];
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struct { unsigned long template:5, slot0:41, slot1a:18,
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slot1b:23, slot2:41; };
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/* NOTE: following doesn't work because bitfields can't cross natural
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size boundaries
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struct { unsigned long template:5, slot0:41, slot1:41, slot2:41; }; */
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} IA64_BUNDLE;
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typedef union U_INST64_A5 {
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IA64_INST inst;
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struct { unsigned long qp:6, r1:7, imm7b:7, r3:2, imm5c:5,
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imm9d:9, s:1, major:4; };
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} INST64_A5;
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typedef union U_INST64_B4 {
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IA64_INST inst;
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struct { unsigned long qp:6, btype:3, un3:3, p:1, b2:3, un11:11, x6:6,
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wh:2, d:1, un1:1, major:4; };
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} INST64_B4;
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typedef union U_INST64_B8 {
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IA64_INST inst;
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struct { unsigned long qp:6, un21:21, x6:6, un4:4, major:4; };
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} INST64_B8;
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typedef union U_INST64_B9 {
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IA64_INST inst;
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struct { unsigned long qp:6, imm20:20, :1, x6:6, :3, i:1, major:4; };
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} INST64_B9;
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typedef union U_INST64_I19 {
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IA64_INST inst;
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struct { unsigned long qp:6, imm20:20, :1, x6:6, x3:3, i:1, major:4; };
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} INST64_I19;
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typedef union U_INST64_I26 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, r2:7, ar3:7, x6:6, x3:3, :1, major:4; };
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} INST64_I26;
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typedef union U_INST64_I27 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, imm:7, ar3:7, x6:6, x3:3, s:1, major:4; };
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} INST64_I27;
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typedef union U_INST64_I28 { /* not privileged (mov from AR) */
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IA64_INST inst;
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struct { unsigned long qp:6, r1:7, :7, ar3:7, x6:6, x3:3, :1, major:4; };
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} INST64_I28;
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typedef union U_INST64_M28 {
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IA64_INST inst;
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struct { unsigned long qp:6, :14, r3:7, x6:6, x3:3, :1, major:4; };
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} INST64_M28;
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typedef union U_INST64_M29 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, r2:7, ar3:7, x6:6, x3:3, :1, major:4; };
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} INST64_M29;
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typedef union U_INST64_M30 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, imm:7, ar3:7, x4:4, x2:2,
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x3:3, s:1, major:4; };
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} INST64_M30;
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typedef union U_INST64_M31 {
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IA64_INST inst;
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struct { unsigned long qp:6, r1:7, :7, ar3:7, x6:6, x3:3, :1, major:4; };
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} INST64_M31;
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typedef union U_INST64_M32 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, r2:7, cr3:7, x6:6, x3:3, :1, major:4; };
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} INST64_M32;
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typedef union U_INST64_M33 {
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IA64_INST inst;
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struct { unsigned long qp:6, r1:7, :7, cr3:7, x6:6, x3:3, :1, major:4; };
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} INST64_M33;
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typedef union U_INST64_M35 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, r2:7, :7, x6:6, x3:3, :1, major:4; };
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} INST64_M35;
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typedef union U_INST64_M36 {
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IA64_INST inst;
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struct { unsigned long qp:6, r1:7, :14, x6:6, x3:3, :1, major:4; };
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} INST64_M36;
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typedef union U_INST64_M37 {
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IA64_INST inst;
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struct { unsigned long qp:6, imm20a:20, :1, x4:4, x2:2, x3:3,
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i:1, major:4; };
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} INST64_M37;
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typedef union U_INST64_M41 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, r2:7, :7, x6:6, x3:3, :1, major:4; };
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} INST64_M41;
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typedef union U_INST64_M42 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, r2:7, r3:7, x6:6, x3:3, :1, major:4; };
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} INST64_M42;
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typedef union U_INST64_M43 {
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IA64_INST inst;
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struct { unsigned long qp:6, r1:7, :7, r3:7, x6:6, x3:3, :1, major:4; };
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} INST64_M43;
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typedef union U_INST64_M44 {
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IA64_INST inst;
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struct { unsigned long qp:6, imm:21, x4:4, i2:2, x3:3, i:1, major:4; };
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} INST64_M44;
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typedef union U_INST64_M45 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, r2:7, r3:7, x6:6, x3:3, :1, major:4; };
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} INST64_M45;
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typedef union U_INST64_M46 {
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IA64_INST inst;
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struct { unsigned long qp:6, r1:7, un7:7, r3:7, x6:6,
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x3:3, un1:1, major:4; };
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} INST64_M46;
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typedef union U_INST64_M47 {
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IA64_INST inst;
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struct { unsigned long qp:6, un14:14, r3:7, x6:6, x3:3, un1:1, major:4; };
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} INST64_M47;
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typedef union U_INST64_M1{
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IA64_INST inst;
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struct { unsigned long qp:6, r1:7, un7:7, r3:7, x:1, hint:2,
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x6:6, m:1, major:4; };
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} INST64_M1;
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typedef union U_INST64_M2{
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IA64_INST inst;
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struct { unsigned long qp:6, r1:7, r2:7, r3:7, x:1, hint:2,
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x6:6, m:1, major:4; };
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} INST64_M2;
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typedef union U_INST64_M3{
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IA64_INST inst;
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struct { unsigned long qp:6, r1:7, imm7:7, r3:7, i:1, hint:2,
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x6:6, s:1, major:4; };
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} INST64_M3;
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typedef union U_INST64_M4 {
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IA64_INST inst;
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struct { unsigned long qp:6, un7:7, r2:7, r3:7, x:1, hint:2,
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x6:6, m:1, major:4; };
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} INST64_M4;
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typedef union U_INST64_M5 {
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IA64_INST inst;
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struct { unsigned long qp:6, imm7:7, r2:7, r3:7, i:1, hint:2,
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x6:6, s:1, major:4; };
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} INST64_M5;
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typedef union U_INST64_M6 {
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IA64_INST inst;
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struct { unsigned long qp:6, f1:7, un7:7, r3:7, x:1, hint:2,
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x6:6, m:1, major:4; };
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} INST64_M6;
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typedef union U_INST64_M9 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, f2:7, r3:7, x:1, hint:2,
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x6:6, m:1, major:4; };
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} INST64_M9;
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typedef union U_INST64_M10 {
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IA64_INST inst;
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struct { unsigned long qp:6, imm7:7, f2:7, r3:7, i:1, hint:2,
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x6:6, s:1, major:4; };
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} INST64_M10;
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typedef union U_INST64_M12 {
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IA64_INST inst;
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struct { unsigned long qp:6, f1:7, f2:7, r3:7, x:1, hint:2,
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x6:6, m:1, major:4; };
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} INST64_M12;
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typedef union U_INST64_M15 {
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IA64_INST inst;
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struct { unsigned long qp:6, :7, imm7:7, r3:7, i:1, hint:2,
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x6:6, s:1, major:4; };
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} INST64_M15;
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typedef union U_INST64 {
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IA64_INST inst;
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struct { unsigned long :37, major:4; } generic;
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INST64_A5 A5; /* used in build_hypercall_bundle only */
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INST64_B4 B4; /* used in build_hypercall_bundle only */
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INST64_B8 B8; /* rfi, bsw.[01] */
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INST64_B9 B9; /* break.b */
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INST64_I19 I19; /* used in build_hypercall_bundle only */
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INST64_I26 I26; /* mov register to ar (I unit) */
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INST64_I27 I27; /* mov immediate to ar (I unit) */
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INST64_I28 I28; /* mov from ar (I unit) */
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INST64_M1 M1; /* ld integer */
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INST64_M2 M2;
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INST64_M3 M3;
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INST64_M4 M4; /* st integer */
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INST64_M5 M5;
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INST64_M6 M6; /* ldfd floating pointer */
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INST64_M9 M9; /* stfd floating pointer */
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INST64_M10 M10; /* stfd floating pointer */
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INST64_M12 M12; /* ldfd pair floating pointer */
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INST64_M15 M15; /* lfetch + imm update */
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INST64_M28 M28; /* purge translation cache entry */
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INST64_M29 M29; /* mov register to ar (M unit) */
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INST64_M30 M30; /* mov immediate to ar (M unit) */
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INST64_M31 M31; /* mov from ar (M unit) */
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INST64_M32 M32; /* mov reg to cr */
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INST64_M33 M33; /* mov from cr */
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INST64_M35 M35; /* mov to psr */
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INST64_M36 M36; /* mov from psr */
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INST64_M37 M37; /* break.m */
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INST64_M41 M41; /* translation cache insert */
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INST64_M42 M42; /* mov to indirect reg/translation reg insert*/
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INST64_M43 M43; /* mov from indirect reg */
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INST64_M44 M44; /* set/reset system mask */
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INST64_M45 M45; /* translation purge */
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INST64_M46 M46; /* translation access (tpa,tak) */
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INST64_M47 M47; /* purge translation entry */
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} INST64;
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#define MASK_41 ((unsigned long)0x1ffffffffff)
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/* Virtual address memory attributes encoding */
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#define VA_MATTR_WB 0x0
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#define VA_MATTR_UC 0x4
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#define VA_MATTR_UCE 0x5
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#define VA_MATTR_WC 0x6
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#define VA_MATTR_NATPAGE 0x7
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#define PMASK(size) (~((size) - 1))
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#define PSIZE(size) (1UL<<(size))
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#define CLEARLSB(ppn, nbits) (((ppn) >> (nbits)) << (nbits))
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#define PAGEALIGN(va, ps) CLEARLSB(va, ps)
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#define PAGE_FLAGS_RV_MASK (0x2|(0x3UL<<50)|(((1UL<<11)-1)<<53))
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#define _PAGE_MA_ST (0x1 << 2) /* is reserved for software use */
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#define ARCH_PAGE_SHIFT 12
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#define INVALID_TI_TAG (1UL << 63)
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#define VTLB_PTE_P_BIT 0
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#define VTLB_PTE_IO_BIT 60
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#define VTLB_PTE_IO (1UL<<VTLB_PTE_IO_BIT)
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#define VTLB_PTE_P (1UL<<VTLB_PTE_P_BIT)
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#define vcpu_quick_region_check(_tr_regions,_ifa) \
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(_tr_regions & (1 << ((unsigned long)_ifa >> 61)))
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#define vcpu_quick_region_set(_tr_regions,_ifa) \
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do {_tr_regions |= (1 << ((unsigned long)_ifa >> 61)); } while (0)
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static inline void vcpu_set_tr(struct thash_data *trp, u64 pte, u64 itir,
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u64 va, u64 rid)
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{
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trp->page_flags = pte;
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trp->itir = itir;
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trp->vadr = va;
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trp->rid = rid;
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}
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extern u64 kvm_get_mpt_entry(u64 gpfn);
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/* Return I/ */
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static inline u64 __gpfn_is_io(u64 gpfn)
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{
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u64 pte;
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pte = kvm_get_mpt_entry(gpfn);
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if (!(pte & GPFN_INV_MASK)) {
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pte = pte & GPFN_IO_MASK;
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if (pte != GPFN_PHYS_MMIO)
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return pte;
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}
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return 0;
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}
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#endif
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#define IA64_NO_FAULT 0
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#define IA64_FAULT 1
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#define VMM_RBS_OFFSET ((VMM_TASK_SIZE + 15) & ~15)
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#define SW_BAD 0 /* Bad mode transitition */
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#define SW_V2P 1 /* Physical emulatino is activated */
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#define SW_P2V 2 /* Exit physical mode emulation */
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#define SW_SELF 3 /* No mode transition */
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#define SW_NOP 4 /* Mode transition, but without action required */
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#define GUEST_IN_PHY 0x1
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#define GUEST_PHY_EMUL 0x2
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#define current_vcpu ((struct kvm_vcpu *) ia64_getreg(_IA64_REG_TP))
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#define VRN_SHIFT 61
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#define VRN_MASK 0xe000000000000000
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#define VRN0 0x0UL
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#define VRN1 0x1UL
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#define VRN2 0x2UL
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#define VRN3 0x3UL
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#define VRN4 0x4UL
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#define VRN5 0x5UL
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#define VRN6 0x6UL
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#define VRN7 0x7UL
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#define IRQ_NO_MASKED 0
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#define IRQ_MASKED_BY_VTPR 1
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#define IRQ_MASKED_BY_INSVC 2 /* masked by inservice IRQ */
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#define PTA_BASE_SHIFT 15
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#define IA64_PSR_VM_BIT 46
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#define IA64_PSR_VM (__IA64_UL(1) << IA64_PSR_VM_BIT)
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/* Interruption Function State */
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#define IA64_IFS_V_BIT 63
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#define IA64_IFS_V (__IA64_UL(1) << IA64_IFS_V_BIT)
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#define PHY_PAGE_UC (_PAGE_A|_PAGE_D|_PAGE_P|_PAGE_MA_UC|_PAGE_AR_RWX)
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#define PHY_PAGE_WB (_PAGE_A|_PAGE_D|_PAGE_P|_PAGE_MA_WB|_PAGE_AR_RWX)
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#ifndef __ASSEMBLY__
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#include <asm/gcc_intrin.h>
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#define is_physical_mode(v) \
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((v->arch.mode_flags) & GUEST_IN_PHY)
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#define is_virtual_mode(v) \
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(!is_physical_mode(v))
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#define MODE_IND(psr) \
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(((psr).it << 2) + ((psr).dt << 1) + (psr).rt)
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#ifndef CONFIG_SMP
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#define _vmm_raw_spin_lock(x) do {}while(0)
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#define _vmm_raw_spin_unlock(x) do {}while(0)
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#else
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#define _vmm_raw_spin_lock(x) \
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do { \
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__u32 *ia64_spinlock_ptr = (__u32 *) (x); \
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__u64 ia64_spinlock_val; \
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ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0);\
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if (unlikely(ia64_spinlock_val)) { \
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do { \
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while (*ia64_spinlock_ptr) \
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ia64_barrier(); \
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ia64_spinlock_val = \
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ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0);\
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} while (ia64_spinlock_val); \
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} \
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} while (0)
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#define _vmm_raw_spin_unlock(x) \
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do { barrier(); \
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((spinlock_t *)x)->raw_lock.lock = 0; } \
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while (0)
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#endif
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void vmm_spin_lock(spinlock_t *lock);
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void vmm_spin_unlock(spinlock_t *lock);
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enum {
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I_TLB = 1,
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D_TLB = 2
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};
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union kvm_va {
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struct {
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unsigned long off : 60; /* intra-region offset */
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unsigned long reg : 4; /* region number */
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} f;
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unsigned long l;
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void *p;
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};
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#define __kvm_pa(x) ({union kvm_va _v; _v.l = (long) (x); \
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_v.f.reg = 0; _v.l; })
|
|
#define __kvm_va(x) ({union kvm_va _v; _v.l = (long) (x); \
|
|
_v.f.reg = -1; _v.p; })
|
|
|
|
#define _REGION_ID(x) ({union ia64_rr _v; _v.val = (long)(x); \
|
|
_v.rid; })
|
|
#define _REGION_PAGE_SIZE(x) ({union ia64_rr _v; _v.val = (long)(x); \
|
|
_v.ps; })
|
|
#define _REGION_HW_WALKER(x) ({union ia64_rr _v; _v.val = (long)(x); \
|
|
_v.ve; })
|
|
|
|
enum vhpt_ref{ DATA_REF, NA_REF, INST_REF, RSE_REF };
|
|
enum tlb_miss_type { INSTRUCTION, DATA, REGISTER };
|
|
|
|
#define VCPU(_v, _x) ((_v)->arch.vpd->_x)
|
|
#define VMX(_v, _x) ((_v)->arch._x)
|
|
|
|
#define VLSAPIC_INSVC(vcpu, i) ((vcpu)->arch.insvc[i])
|
|
#define VLSAPIC_XTP(_v) VMX(_v, xtp)
|
|
|
|
static inline unsigned long itir_ps(unsigned long itir)
|
|
{
|
|
return ((itir >> 2) & 0x3f);
|
|
}
|
|
|
|
|
|
/**************************************************************************
|
|
VCPU control register access routines
|
|
**************************************************************************/
|
|
|
|
static inline u64 vcpu_get_itir(struct kvm_vcpu *vcpu)
|
|
{
|
|
return ((u64)VCPU(vcpu, itir));
|
|
}
|
|
|
|
static inline void vcpu_set_itir(struct kvm_vcpu *vcpu, u64 val)
|
|
{
|
|
VCPU(vcpu, itir) = val;
|
|
}
|
|
|
|
static inline u64 vcpu_get_ifa(struct kvm_vcpu *vcpu)
|
|
{
|
|
return ((u64)VCPU(vcpu, ifa));
|
|
}
|
|
|
|
static inline void vcpu_set_ifa(struct kvm_vcpu *vcpu, u64 val)
|
|
{
|
|
VCPU(vcpu, ifa) = val;
|
|
}
|
|
|
|
static inline u64 vcpu_get_iva(struct kvm_vcpu *vcpu)
|
|
{
|
|
return ((u64)VCPU(vcpu, iva));
|
|
}
|
|
|
|
static inline u64 vcpu_get_pta(struct kvm_vcpu *vcpu)
|
|
{
|
|
return ((u64)VCPU(vcpu, pta));
|
|
}
|
|
|
|
static inline u64 vcpu_get_lid(struct kvm_vcpu *vcpu)
|
|
{
|
|
return ((u64)VCPU(vcpu, lid));
|
|
}
|
|
|
|
static inline u64 vcpu_get_tpr(struct kvm_vcpu *vcpu)
|
|
{
|
|
return ((u64)VCPU(vcpu, tpr));
|
|
}
|
|
|
|
static inline u64 vcpu_get_eoi(struct kvm_vcpu *vcpu)
|
|
{
|
|
return (0UL); /*reads of eoi always return 0 */
|
|
}
|
|
|
|
static inline u64 vcpu_get_irr0(struct kvm_vcpu *vcpu)
|
|
{
|
|
return ((u64)VCPU(vcpu, irr[0]));
|
|
}
|
|
|
|
static inline u64 vcpu_get_irr1(struct kvm_vcpu *vcpu)
|
|
{
|
|
return ((u64)VCPU(vcpu, irr[1]));
|
|
}
|
|
|
|
static inline u64 vcpu_get_irr2(struct kvm_vcpu *vcpu)
|
|
{
|
|
return ((u64)VCPU(vcpu, irr[2]));
|
|
}
|
|
|
|
static inline u64 vcpu_get_irr3(struct kvm_vcpu *vcpu)
|
|
{
|
|
return ((u64)VCPU(vcpu, irr[3]));
|
|
}
|
|
|
|
static inline void vcpu_set_dcr(struct kvm_vcpu *vcpu, u64 val)
|
|
{
|
|
ia64_setreg(_IA64_REG_CR_DCR, val);
|
|
}
|
|
|
|
static inline void vcpu_set_isr(struct kvm_vcpu *vcpu, u64 val)
|
|
{
|
|
VCPU(vcpu, isr) = val;
|
|
}
|
|
|
|
static inline void vcpu_set_lid(struct kvm_vcpu *vcpu, u64 val)
|
|
{
|
|
VCPU(vcpu, lid) = val;
|
|
}
|
|
|
|
static inline void vcpu_set_ipsr(struct kvm_vcpu *vcpu, u64 val)
|
|
{
|
|
VCPU(vcpu, ipsr) = val;
|
|
}
|
|
|
|
static inline void vcpu_set_iip(struct kvm_vcpu *vcpu, u64 val)
|
|
{
|
|
VCPU(vcpu, iip) = val;
|
|
}
|
|
|
|
static inline void vcpu_set_ifs(struct kvm_vcpu *vcpu, u64 val)
|
|
{
|
|
VCPU(vcpu, ifs) = val;
|
|
}
|
|
|
|
static inline void vcpu_set_iipa(struct kvm_vcpu *vcpu, u64 val)
|
|
{
|
|
VCPU(vcpu, iipa) = val;
|
|
}
|
|
|
|
static inline void vcpu_set_iha(struct kvm_vcpu *vcpu, u64 val)
|
|
{
|
|
VCPU(vcpu, iha) = val;
|
|
}
|
|
|
|
|
|
static inline u64 vcpu_get_rr(struct kvm_vcpu *vcpu, u64 reg)
|
|
{
|
|
return vcpu->arch.vrr[reg>>61];
|
|
}
|
|
|
|
/**************************************************************************
|
|
VCPU debug breakpoint register access routines
|
|
**************************************************************************/
|
|
|
|
static inline void vcpu_set_dbr(struct kvm_vcpu *vcpu, u64 reg, u64 val)
|
|
{
|
|
__ia64_set_dbr(reg, val);
|
|
}
|
|
|
|
static inline void vcpu_set_ibr(struct kvm_vcpu *vcpu, u64 reg, u64 val)
|
|
{
|
|
ia64_set_ibr(reg, val);
|
|
}
|
|
|
|
static inline u64 vcpu_get_dbr(struct kvm_vcpu *vcpu, u64 reg)
|
|
{
|
|
return ((u64)__ia64_get_dbr(reg));
|
|
}
|
|
|
|
static inline u64 vcpu_get_ibr(struct kvm_vcpu *vcpu, u64 reg)
|
|
{
|
|
return ((u64)ia64_get_ibr(reg));
|
|
}
|
|
|
|
/**************************************************************************
|
|
VCPU performance monitor register access routines
|
|
**************************************************************************/
|
|
static inline void vcpu_set_pmc(struct kvm_vcpu *vcpu, u64 reg, u64 val)
|
|
{
|
|
/* NOTE: Writes to unimplemented PMC registers are discarded */
|
|
ia64_set_pmc(reg, val);
|
|
}
|
|
|
|
static inline void vcpu_set_pmd(struct kvm_vcpu *vcpu, u64 reg, u64 val)
|
|
{
|
|
/* NOTE: Writes to unimplemented PMD registers are discarded */
|
|
ia64_set_pmd(reg, val);
|
|
}
|
|
|
|
static inline u64 vcpu_get_pmc(struct kvm_vcpu *vcpu, u64 reg)
|
|
{
|
|
/* NOTE: Reads from unimplemented PMC registers return zero */
|
|
return ((u64)ia64_get_pmc(reg));
|
|
}
|
|
|
|
static inline u64 vcpu_get_pmd(struct kvm_vcpu *vcpu, u64 reg)
|
|
{
|
|
/* NOTE: Reads from unimplemented PMD registers return zero */
|
|
return ((u64)ia64_get_pmd(reg));
|
|
}
|
|
|
|
static inline unsigned long vrrtomrr(unsigned long val)
|
|
{
|
|
union ia64_rr rr;
|
|
rr.val = val;
|
|
rr.rid = (rr.rid << 4) | 0xe;
|
|
if (rr.ps > PAGE_SHIFT)
|
|
rr.ps = PAGE_SHIFT;
|
|
rr.ve = 1;
|
|
return rr.val;
|
|
}
|
|
|
|
|
|
static inline int highest_bits(int *dat)
|
|
{
|
|
u32 bits, bitnum;
|
|
int i;
|
|
|
|
/* loop for all 256 bits */
|
|
for (i = 7; i >= 0 ; i--) {
|
|
bits = dat[i];
|
|
if (bits) {
|
|
bitnum = fls(bits);
|
|
return i * 32 + bitnum - 1;
|
|
}
|
|
}
|
|
return NULL_VECTOR;
|
|
}
|
|
|
|
/*
|
|
* The pending irq is higher than the inservice one.
|
|
*
|
|
*/
|
|
static inline int is_higher_irq(int pending, int inservice)
|
|
{
|
|
return ((pending > inservice)
|
|
|| ((pending != NULL_VECTOR)
|
|
&& (inservice == NULL_VECTOR)));
|
|
}
|
|
|
|
static inline int is_higher_class(int pending, int mic)
|
|
{
|
|
return ((pending >> 4) > mic);
|
|
}
|
|
|
|
/*
|
|
* Return 0-255 for pending irq.
|
|
* NULL_VECTOR: when no pending.
|
|
*/
|
|
static inline int highest_pending_irq(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (VCPU(vcpu, irr[0]) & (1UL<<NMI_VECTOR))
|
|
return NMI_VECTOR;
|
|
if (VCPU(vcpu, irr[0]) & (1UL<<ExtINT_VECTOR))
|
|
return ExtINT_VECTOR;
|
|
|
|
return highest_bits((int *)&VCPU(vcpu, irr[0]));
|
|
}
|
|
|
|
static inline int highest_inservice_irq(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (VMX(vcpu, insvc[0]) & (1UL<<NMI_VECTOR))
|
|
return NMI_VECTOR;
|
|
if (VMX(vcpu, insvc[0]) & (1UL<<ExtINT_VECTOR))
|
|
return ExtINT_VECTOR;
|
|
|
|
return highest_bits((int *)&(VMX(vcpu, insvc[0])));
|
|
}
|
|
|
|
extern void vcpu_get_fpreg(struct kvm_vcpu *vcpu, u64 reg,
|
|
struct ia64_fpreg *val);
|
|
extern void vcpu_set_fpreg(struct kvm_vcpu *vcpu, u64 reg,
|
|
struct ia64_fpreg *val);
|
|
extern u64 vcpu_get_gr(struct kvm_vcpu *vcpu, u64 reg);
|
|
extern void vcpu_set_gr(struct kvm_vcpu *vcpu, u64 reg, u64 val, int nat);
|
|
extern u64 vcpu_get_psr(struct kvm_vcpu *vcpu);
|
|
extern void vcpu_set_psr(struct kvm_vcpu *vcpu, u64 val);
|
|
extern u64 vcpu_thash(struct kvm_vcpu *vcpu, u64 vadr);
|
|
extern void vcpu_bsw0(struct kvm_vcpu *vcpu);
|
|
extern void thash_vhpt_insert(struct kvm_vcpu *v, u64 pte,
|
|
u64 itir, u64 va, int type);
|
|
extern struct thash_data *vhpt_lookup(u64 va);
|
|
extern u64 guest_vhpt_lookup(u64 iha, u64 *pte);
|
|
extern void thash_purge_entries(struct kvm_vcpu *v, u64 va, u64 ps);
|
|
extern void thash_purge_entries_remote(struct kvm_vcpu *v, u64 va, u64 ps);
|
|
extern u64 translate_phy_pte(u64 *pte, u64 itir, u64 va);
|
|
extern int thash_purge_and_insert(struct kvm_vcpu *v, u64 pte,
|
|
u64 itir, u64 ifa, int type);
|
|
extern void thash_purge_all(struct kvm_vcpu *v);
|
|
extern struct thash_data *vtlb_lookup(struct kvm_vcpu *v,
|
|
u64 va, int is_data);
|
|
extern int vtr_find_overlap(struct kvm_vcpu *vcpu, u64 va,
|
|
u64 ps, int is_data);
|
|
|
|
extern void vcpu_increment_iip(struct kvm_vcpu *v);
|
|
extern void vcpu_decrement_iip(struct kvm_vcpu *vcpu);
|
|
extern void vcpu_pend_interrupt(struct kvm_vcpu *vcpu, u8 vec);
|
|
extern void vcpu_unpend_interrupt(struct kvm_vcpu *vcpu, u8 vec);
|
|
extern void data_page_not_present(struct kvm_vcpu *vcpu, u64 vadr);
|
|
extern void dnat_page_consumption(struct kvm_vcpu *vcpu, u64 vadr);
|
|
extern void alt_dtlb(struct kvm_vcpu *vcpu, u64 vadr);
|
|
extern void nested_dtlb(struct kvm_vcpu *vcpu);
|
|
extern void dvhpt_fault(struct kvm_vcpu *vcpu, u64 vadr);
|
|
extern int vhpt_enabled(struct kvm_vcpu *vcpu, u64 vadr, enum vhpt_ref ref);
|
|
|
|
extern void update_vhpi(struct kvm_vcpu *vcpu, int vec);
|
|
extern int irq_masked(struct kvm_vcpu *vcpu, int h_pending, int h_inservice);
|
|
|
|
extern int fetch_code(struct kvm_vcpu *vcpu, u64 gip, IA64_BUNDLE *pbundle);
|
|
extern void emulate_io_inst(struct kvm_vcpu *vcpu, u64 padr, u64 ma);
|
|
extern void vmm_transition(struct kvm_vcpu *vcpu);
|
|
extern void vmm_trampoline(union context *from, union context *to);
|
|
extern int vmm_entry(void);
|
|
extern u64 vcpu_get_itc(struct kvm_vcpu *vcpu);
|
|
|
|
extern void vmm_reset_entry(void);
|
|
void kvm_init_vtlb(struct kvm_vcpu *v);
|
|
void kvm_init_vhpt(struct kvm_vcpu *v);
|
|
void thash_init(struct thash_cb *hcb, u64 sz);
|
|
|
|
void panic_vm(struct kvm_vcpu *v, const char *fmt, ...);
|
|
|
|
extern u64 ia64_call_vsa(u64 proc, u64 arg1, u64 arg2, u64 arg3,
|
|
u64 arg4, u64 arg5, u64 arg6, u64 arg7);
|
|
|
|
extern long vmm_sanity;
|
|
|
|
#endif
|
|
#endif /* __VCPU_H__ */
|