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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Linus Torvalds](/assets/img/avatar_default.png)
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
185 lines
5.7 KiB
ArmAsm
185 lines
5.7 KiB
ArmAsm
/*
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* McKinley-optimized version of copy_page().
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*
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* Copyright (C) 2002 Hewlett-Packard Co
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* David Mosberger <davidm@hpl.hp.com>
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*
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* Inputs:
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* in0: address of target page
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* in1: address of source page
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* Output:
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* no return value
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*
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* General idea:
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* - use regular loads and stores to prefetch data to avoid consuming M-slot just for
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* lfetches => good for in-cache performance
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* - avoid l2 bank-conflicts by not storing into the same 16-byte bank within a single
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* cycle
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*
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* Principle of operation:
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* First, note that L1 has a line-size of 64 bytes and L2 a line-size of 128 bytes.
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* To avoid secondary misses in L2, we prefetch both source and destination with a line-size
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* of 128 bytes. When both of these lines are in the L2 and the first half of the
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* source line is in L1, we start copying the remaining words. The second half of the
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* source line is prefetched in an earlier iteration, so that by the time we start
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* accessing it, it's also present in the L1.
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*
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* We use a software-pipelined loop to control the overall operation. The pipeline
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* has 2*PREFETCH_DIST+K stages. The first PREFETCH_DIST stages are used for prefetching
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* source cache-lines. The second PREFETCH_DIST stages are used for prefetching destination
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* cache-lines, the last K stages are used to copy the cache-line words not copied by
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* the prefetches. The four relevant points in the pipelined are called A, B, C, D:
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* p[A] is TRUE if a source-line should be prefetched, p[B] is TRUE if a destination-line
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* should be prefetched, p[C] is TRUE if the second half of an L2 line should be brought
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* into L1D and p[D] is TRUE if a cacheline needs to be copied.
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*
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* This all sounds very complicated, but thanks to the modulo-scheduled loop support,
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* the resulting code is very regular and quite easy to follow (once you get the idea).
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*
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* As a secondary optimization, the first 2*PREFETCH_DIST iterations are implemented
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* as the separate .prefetch_loop. Logically, this loop performs exactly like the
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* main-loop (.line_copy), but has all known-to-be-predicated-off instructions removed,
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* so that each loop iteration is faster (again, good for cached case).
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*
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* When reading the code, it helps to keep the following picture in mind:
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*
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* word 0 word 1
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* +------+------+---
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* | v[x] | t1 | ^
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* | t2 | t3 | |
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* | t4 | t5 | |
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* | t6 | t7 | | 128 bytes
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* | n[y] | t9 | | (L2 cache line)
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* | t10 | t11 | |
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* | t12 | t13 | |
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* | t14 | t15 | v
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* +------+------+---
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*
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* Here, v[x] is copied by the (memory) prefetch. n[y] is loaded at p[C]
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* to fetch the second-half of the L2 cache line into L1, and the tX words are copied in
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* an order that avoids bank conflicts.
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*/
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#include <asm/asmmacro.h>
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#include <asm/page.h>
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#define PREFETCH_DIST 8 // McKinley sustains 16 outstanding L2 misses (8 ld, 8 st)
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#define src0 r2
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#define src1 r3
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#define dst0 r9
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#define dst1 r10
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#define src_pre_mem r11
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#define dst_pre_mem r14
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#define src_pre_l2 r15
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#define dst_pre_l2 r16
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#define t1 r17
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#define t2 r18
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#define t3 r19
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#define t4 r20
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#define t5 t1 // alias!
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#define t6 t2 // alias!
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#define t7 t3 // alias!
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#define t9 t5 // alias!
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#define t10 t4 // alias!
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#define t11 t7 // alias!
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#define t12 t6 // alias!
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#define t14 t10 // alias!
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#define t13 r21
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#define t15 r22
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#define saved_lc r23
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#define saved_pr r24
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#define A 0
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#define B (PREFETCH_DIST)
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#define C (B + PREFETCH_DIST)
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#define D (C + 3)
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#define N (D + 1)
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#define Nrot ((N + 7) & ~7)
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GLOBAL_ENTRY(copy_page)
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.prologue
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alloc r8 = ar.pfs, 2, Nrot-2, 0, Nrot
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.rotr v[2*PREFETCH_DIST], n[D-C+1]
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.rotp p[N]
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.save ar.lc, saved_lc
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mov saved_lc = ar.lc
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.save pr, saved_pr
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mov saved_pr = pr
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.body
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mov src_pre_mem = in1
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mov pr.rot = 0x10000
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mov ar.ec = 1 // special unrolled loop
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mov dst_pre_mem = in0
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mov ar.lc = 2*PREFETCH_DIST - 1
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add src_pre_l2 = 8*8, in1
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add dst_pre_l2 = 8*8, in0
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add src0 = 8, in1 // first t1 src
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add src1 = 3*8, in1 // first t3 src
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add dst0 = 8, in0 // first t1 dst
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add dst1 = 3*8, in0 // first t3 dst
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mov t1 = (PAGE_SIZE/128) - (2*PREFETCH_DIST) - 1
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nop.m 0
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nop.i 0
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;;
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// same as .line_copy loop, but with all predicated-off instructions removed:
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.prefetch_loop:
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(p[A]) ld8 v[A] = [src_pre_mem], 128 // M0
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(p[B]) st8 [dst_pre_mem] = v[B], 128 // M2
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br.ctop.sptk .prefetch_loop
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;;
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cmp.eq p16, p0 = r0, r0 // reset p16 to 1 (br.ctop cleared it to zero)
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mov ar.lc = t1 // with 64KB pages, t1 is too big to fit in 8 bits!
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mov ar.ec = N // # of stages in pipeline
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;;
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.line_copy:
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(p[D]) ld8 t2 = [src0], 3*8 // M0
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(p[D]) ld8 t4 = [src1], 3*8 // M1
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(p[B]) st8 [dst_pre_mem] = v[B], 128 // M2 prefetch dst from memory
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(p[D]) st8 [dst_pre_l2] = n[D-C], 128 // M3 prefetch dst from L2
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;;
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(p[A]) ld8 v[A] = [src_pre_mem], 128 // M0 prefetch src from memory
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(p[C]) ld8 n[0] = [src_pre_l2], 128 // M1 prefetch src from L2
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(p[D]) st8 [dst0] = t1, 8 // M2
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(p[D]) st8 [dst1] = t3, 8 // M3
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;;
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(p[D]) ld8 t5 = [src0], 8
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(p[D]) ld8 t7 = [src1], 3*8
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(p[D]) st8 [dst0] = t2, 3*8
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(p[D]) st8 [dst1] = t4, 3*8
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;;
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(p[D]) ld8 t6 = [src0], 3*8
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(p[D]) ld8 t10 = [src1], 8
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(p[D]) st8 [dst0] = t5, 8
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(p[D]) st8 [dst1] = t7, 3*8
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;;
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(p[D]) ld8 t9 = [src0], 3*8
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(p[D]) ld8 t11 = [src1], 3*8
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(p[D]) st8 [dst0] = t6, 3*8
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(p[D]) st8 [dst1] = t10, 8
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;;
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(p[D]) ld8 t12 = [src0], 8
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(p[D]) ld8 t14 = [src1], 8
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(p[D]) st8 [dst0] = t9, 3*8
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(p[D]) st8 [dst1] = t11, 3*8
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;;
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(p[D]) ld8 t13 = [src0], 4*8
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(p[D]) ld8 t15 = [src1], 4*8
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(p[D]) st8 [dst0] = t12, 8
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(p[D]) st8 [dst1] = t14, 8
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;;
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(p[D-1])ld8 t1 = [src0], 8
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(p[D-1])ld8 t3 = [src1], 8
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(p[D]) st8 [dst0] = t13, 4*8
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(p[D]) st8 [dst1] = t15, 4*8
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br.ctop.sptk .line_copy
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;;
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mov ar.lc = saved_lc
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mov pr = saved_pr, -1
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br.ret.sptk.many rp
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END(copy_page)
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