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![Harvey Harrison](/assets/img/avatar_default.png)
drivers/video/carminefb.c:171:41: warning: cast to restricted __be32 Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Cc: Sebastian Siewior <bigeasy@linutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
790 lines
22 KiB
C
790 lines
22 KiB
C
/*
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* Frame buffer driver for the Carmine GPU.
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*
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* The driver configures the GPU as follows
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* - FB0 is display 0 with unique memory area
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* - FB1 is display 1 with unique memory area
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* - both display use 32 bit colors
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/fb.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include "carminefb.h"
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#include "carminefb_regs.h"
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#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
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#error "The endianness of the target host has not been defined."
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#endif
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/*
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* The initial video mode can be supplied via two different ways:
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* - as a string that is passed to fb_find_mode() (module option fb_mode_str)
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* - as an integer that picks the video mode from carmine_modedb[] (module
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* option fb_mode)
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*
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* If nothing is used than the initial video mode will be the
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* CARMINEFB_DEFAULT_VIDEO_MODE member of the carmine_modedb[].
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*/
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#define CARMINEFB_DEFAULT_VIDEO_MODE 1
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static unsigned int fb_mode = CARMINEFB_DEFAULT_VIDEO_MODE;
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module_param(fb_mode, uint, 444);
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MODULE_PARM_DESC(fb_mode, "Initial video mode as integer.");
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static char *fb_mode_str;
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module_param(fb_mode_str, charp, 444);
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MODULE_PARM_DESC(fb_mode_str, "Initial video mode in characters.");
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/*
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* Carminefb displays:
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* 0b000 None
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* 0b001 Display 0
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* 0b010 Display 1
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*/
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static int fb_displays = CARMINE_USE_DISPLAY0 | CARMINE_USE_DISPLAY1;
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module_param(fb_displays, int, 444);
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MODULE_PARM_DESC(fb_displays, "Bit mode, which displays are used");
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struct carmine_hw {
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void __iomem *v_regs;
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void __iomem *screen_mem;
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struct fb_info *fb[MAX_DISPLAY];
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};
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struct carmine_resolution {
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u32 htp;
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u32 hsp;
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u32 hsw;
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u32 hdp;
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u32 vtr;
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u32 vsp;
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u32 vsw;
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u32 vdp;
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u32 disp_mode;
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};
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struct carmine_fb {
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void __iomem *display_reg;
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void __iomem *screen_base;
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u32 smem_offset;
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u32 cur_mode;
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u32 new_mode;
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struct carmine_resolution *res;
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u32 pseudo_palette[16];
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};
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static struct fb_fix_screeninfo carminefb_fix __devinitdata = {
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.id = "Carmine",
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.type = FB_TYPE_PACKED_PIXELS,
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.visual = FB_VISUAL_TRUECOLOR,
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.accel = FB_ACCEL_NONE,
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};
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static const struct fb_videomode carmine_modedb[] = {
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{
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.name = "640x480",
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.xres = 640,
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.yres = 480,
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}, {
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.name = "800x600",
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.xres = 800,
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.yres = 600,
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},
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};
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static struct carmine_resolution car_modes[] = {
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{
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/* 640x480 */
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.htp = 800,
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.hsp = 672,
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.hsw = 96,
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.hdp = 640,
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.vtr = 525,
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.vsp = 490,
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.vsw = 2,
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.vdp = 480,
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.disp_mode = 0x1400,
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},
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{
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/* 800x600 */
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.htp = 1060,
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.hsp = 864,
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.hsw = 72,
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.hdp = 800,
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.vtr = 628,
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.vsp = 601,
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.vsw = 2,
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.vdp = 600,
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.disp_mode = 0x0d00,
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}
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};
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static int carmine_find_mode(const struct fb_var_screeninfo *var)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(car_modes); i++)
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if (car_modes[i].hdp == var->xres &&
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car_modes[i].vdp == var->yres)
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return i;
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return -EINVAL;
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}
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static void c_set_disp_reg(const struct carmine_fb *par,
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u32 offset, u32 val)
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{
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writel(val, par->display_reg + offset);
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}
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static u32 c_get_disp_reg(const struct carmine_fb *par,
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u32 offset)
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{
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return readl(par->display_reg + offset);
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}
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static void c_set_hw_reg(const struct carmine_hw *hw,
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u32 offset, u32 val)
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{
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writel(val, hw->v_regs + offset);
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}
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static u32 c_get_hw_reg(const struct carmine_hw *hw,
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u32 offset)
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{
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return readl(hw->v_regs + offset);
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}
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static int carmine_setcolreg(unsigned regno, unsigned red, unsigned green,
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unsigned blue, unsigned transp, struct fb_info *info)
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{
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if (regno >= 16)
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return 1;
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red >>= 8;
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green >>= 8;
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blue >>= 8;
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transp >>= 8;
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((__be32 *)info->pseudo_palette)[regno] = cpu_to_be32(transp << 24 |
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red << 0 | green << 8 | blue << 16);
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return 0;
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}
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static int carmine_check_var(struct fb_var_screeninfo *var,
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struct fb_info *info)
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{
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int ret;
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ret = carmine_find_mode(var);
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if (ret < 0)
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return ret;
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if (var->grayscale || var->rotate || var->nonstd)
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return -EINVAL;
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var->xres_virtual = var->xres;
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var->yres_virtual = var->yres;
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var->bits_per_pixel = 32;
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#ifdef __BIG_ENDIAN
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var->transp.offset = 24;
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var->red.offset = 0;
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var->green.offset = 8;
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var->blue.offset = 16;
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#else
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var->transp.offset = 24;
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var->red.offset = 16;
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var->green.offset = 8;
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var->blue.offset = 0;
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#endif
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var->red.length = 8;
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var->green.length = 8;
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var->blue.length = 8;
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var->transp.length = 8;
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var->red.msb_right = 0;
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var->green.msb_right = 0;
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var->blue.msb_right = 0;
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var->transp.msb_right = 0;
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return 0;
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}
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static void carmine_init_display_param(struct carmine_fb *par)
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{
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u32 width;
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u32 height;
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u32 param;
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u32 window_size;
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u32 soffset = par->smem_offset;
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c_set_disp_reg(par, CARMINE_DISP_REG_C_TRANS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_MLMR_TRANS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_CURSOR_MODE,
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CARMINE_CURSOR0_PRIORITY_MASK |
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CARMINE_CURSOR1_PRIORITY_MASK |
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CARMINE_CURSOR_CUTZ_MASK);
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/* Set default cursor position */
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c_set_disp_reg(par, CARMINE_DISP_REG_CUR1_POS, 0 << 16 | 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_CUR2_POS, 0 << 16 | 0);
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/* Set default display mode */
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c_set_disp_reg(par, CARMINE_DISP_REG_L0_EXT_MODE, CARMINE_WINDOW_MODE |
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CARMINE_EXT_CMODE_DIRECT24_RGBA);
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c_set_disp_reg(par, CARMINE_DISP_REG_L1_EXT_MODE,
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CARMINE_EXT_CMODE_DIRECT24_RGBA);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2_EXT_MODE, CARMINE_EXTEND_MODE |
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CARMINE_EXT_CMODE_DIRECT24_RGBA);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3_EXT_MODE, CARMINE_EXTEND_MODE |
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CARMINE_EXT_CMODE_DIRECT24_RGBA);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4_EXT_MODE, CARMINE_EXTEND_MODE |
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CARMINE_EXT_CMODE_DIRECT24_RGBA);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5_EXT_MODE, CARMINE_EXTEND_MODE |
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CARMINE_EXT_CMODE_DIRECT24_RGBA);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6_EXT_MODE, CARMINE_EXTEND_MODE |
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CARMINE_EXT_CMODE_DIRECT24_RGBA);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7_EXT_MODE, CARMINE_EXTEND_MODE |
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CARMINE_EXT_CMODE_DIRECT24_RGBA);
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/* Set default frame size to layer mode register */
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width = par->res->hdp * 4 / CARMINE_DISP_WIDTH_UNIT;
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width = width << CARMINE_DISP_WIDTH_SHIFT;
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height = par->res->vdp - 1;
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param = width | height;
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c_set_disp_reg(par, CARMINE_DISP_REG_L0_MODE_W_H, param);
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c_set_disp_reg(par, CARMINE_DISP_REG_L1_WIDTH, width);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2_MODE_W_H, param);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3_MODE_W_H, param);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4_MODE_W_H, param);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5_MODE_W_H, param);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6_MODE_W_H, param);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7_MODE_W_H, param);
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/* Set default pos and size */
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window_size = (par->res->vdp - 1) << CARMINE_DISP_WIN_H_SHIFT;
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window_size |= par->res->hdp;
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c_set_disp_reg(par, CARMINE_DISP_REG_L0_WIN_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L0_WIN_SIZE, window_size);
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c_set_disp_reg(par, CARMINE_DISP_REG_L1_WIN_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L1_WIN_SIZE, window_size);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2_WIN_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2_WIN_SIZE, window_size);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3_WIN_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3_WIN_SIZE, window_size);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4_WIN_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4_WIN_SIZE, window_size);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5_WIN_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5_WIN_SIZE, window_size);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6_WIN_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6_WIN_SIZE, window_size);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7_WIN_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7_WIN_SIZE, window_size);
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/* Set default origin address */
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c_set_disp_reg(par, CARMINE_DISP_REG_L0_ORG_ADR, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L1_ORG_ADR, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2_ORG_ADR1, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3_ORG_ADR1, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4_ORG_ADR1, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5_ORG_ADR1, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6_ORG_ADR1, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7_ORG_ADR1, soffset);
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/* Set default display address */
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c_set_disp_reg(par, CARMINE_DISP_REG_L0_DISP_ADR, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2_DISP_ADR1, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3_DISP_ADR1, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4_DISP_ADR1, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5_DISP_ADR1, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6_DISP_ADR0, soffset);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7_DISP_ADR0, soffset);
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/* Set default display position */
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c_set_disp_reg(par, CARMINE_DISP_REG_L0_DISP_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2_DISP_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3_DISP_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4_DISP_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5_DISP_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6_DISP_POS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7_DISP_POS, 0);
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/* Set default blend mode */
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c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L0, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L1, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L2, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L3, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L4, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L5, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L6, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L7, 0);
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/* default transparency mode */
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c_set_disp_reg(par, CARMINE_DISP_REG_L0_TRANS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L1_TRANS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2_TRANS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3_TRANS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4_TRANS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5_TRANS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6_TRANS, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7_TRANS, 0);
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/* Set default read skip parameter */
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c_set_disp_reg(par, CARMINE_DISP_REG_L0RM, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2RM, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3RM, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4RM, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5RM, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6RM, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7RM, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L0PX, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2PX, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3PX, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4PX, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5PX, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6PX, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7PX, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L0PY, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L2PY, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L3PY, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L4PY, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L5PY, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L6PY, 0);
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c_set_disp_reg(par, CARMINE_DISP_REG_L7PY, 0);
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}
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static void set_display_parameters(struct carmine_fb *par)
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{
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u32 mode;
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u32 hdp, vdp, htp, hsp, hsw, vtr, vsp, vsw;
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/*
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* display timing. Parameters are decreased by one because hardware
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* spec is 0 to (n - 1)
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* */
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hdp = par->res->hdp - 1;
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vdp = par->res->vdp - 1;
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htp = par->res->htp - 1;
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hsp = par->res->hsp - 1;
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hsw = par->res->hsw - 1;
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vtr = par->res->vtr - 1;
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vsp = par->res->vsp - 1;
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vsw = par->res->vsw - 1;
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c_set_disp_reg(par, CARMINE_DISP_REG_H_TOTAL,
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htp << CARMINE_DISP_HTP_SHIFT);
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c_set_disp_reg(par, CARMINE_DISP_REG_H_PERIOD,
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(hdp << CARMINE_DISP_HDB_SHIFT) | hdp);
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c_set_disp_reg(par, CARMINE_DISP_REG_V_H_W_H_POS,
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(vsw << CARMINE_DISP_VSW_SHIFT) |
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|
(hsw << CARMINE_DISP_HSW_SHIFT) |
|
|
(hsp));
|
|
c_set_disp_reg(par, CARMINE_DISP_REG_V_TOTAL,
|
|
vtr << CARMINE_DISP_VTR_SHIFT);
|
|
c_set_disp_reg(par, CARMINE_DISP_REG_V_PERIOD_POS,
|
|
(vdp << CARMINE_DISP_VDP_SHIFT) | vsp);
|
|
|
|
/* clock */
|
|
mode = c_get_disp_reg(par, CARMINE_DISP_REG_DCM1);
|
|
mode = (mode & ~CARMINE_DISP_DCM_MASK) |
|
|
(par->res->disp_mode & CARMINE_DISP_DCM_MASK);
|
|
/* enable video output and layer 0 */
|
|
mode |= CARMINE_DEN | CARMINE_L0E;
|
|
c_set_disp_reg(par, CARMINE_DISP_REG_DCM1, mode);
|
|
}
|
|
|
|
static int carmine_set_par(struct fb_info *info)
|
|
{
|
|
struct carmine_fb *par = info->par;
|
|
int ret;
|
|
|
|
ret = carmine_find_mode(&info->var);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
par->new_mode = ret;
|
|
if (par->cur_mode != par->new_mode) {
|
|
|
|
par->cur_mode = par->new_mode;
|
|
par->res = &car_modes[par->new_mode];
|
|
|
|
carmine_init_display_param(par);
|
|
set_display_parameters(par);
|
|
}
|
|
|
|
info->fix.line_length = info->var.xres * info->var.bits_per_pixel / 8;
|
|
return 0;
|
|
}
|
|
|
|
static int init_hardware(struct carmine_hw *hw)
|
|
{
|
|
u32 flags;
|
|
u32 loops;
|
|
u32 ret;
|
|
|
|
/* Initalize Carmine */
|
|
/* Sets internal clock */
|
|
c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_CLOCK_ENABLE,
|
|
CARMINE_DFLT_IP_CLOCK_ENABLE);
|
|
|
|
/* Video signal output is turned off */
|
|
c_set_hw_reg(hw, CARMINE_DISP0_REG + CARMINE_DISP_REG_DCM1, 0);
|
|
c_set_hw_reg(hw, CARMINE_DISP1_REG + CARMINE_DISP_REG_DCM1, 0);
|
|
|
|
/* Software reset */
|
|
c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_SOFTWARE_RESET, 1);
|
|
c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_SOFTWARE_RESET, 0);
|
|
|
|
/* I/O mode settings */
|
|
flags = CARMINE_DFLT_IP_DCTL_IO_CONT1 << 16 |
|
|
CARMINE_DFLT_IP_DCTL_IO_CONT0;
|
|
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_IOCONT1_IOCONT0,
|
|
flags);
|
|
|
|
/* DRAM initial sequence */
|
|
flags = CARMINE_DFLT_IP_DCTL_MODE << 16 | CARMINE_DFLT_IP_DCTL_ADD;
|
|
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_MODE_ADD,
|
|
flags);
|
|
|
|
flags = CARMINE_DFLT_IP_DCTL_SET_TIME1 << 16 |
|
|
CARMINE_DFLT_IP_DCTL_EMODE;
|
|
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_SETTIME1_EMODE,
|
|
flags);
|
|
|
|
flags = CARMINE_DFLT_IP_DCTL_REFRESH << 16 |
|
|
CARMINE_DFLT_IP_DCTL_SET_TIME2;
|
|
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_REFRESH_SETTIME2,
|
|
flags);
|
|
|
|
flags = CARMINE_DFLT_IP_DCTL_RESERVE2 << 16 |
|
|
CARMINE_DFLT_IP_DCTL_FIFO_DEPTH;
|
|
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_RSV2_RSV1, flags);
|
|
|
|
flags = CARMINE_DFLT_IP_DCTL_DDRIF2 << 16 | CARMINE_DFLT_IP_DCTL_DDRIF1;
|
|
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_DDRIF2_DDRIF1,
|
|
flags);
|
|
|
|
flags = CARMINE_DFLT_IP_DCTL_RESERVE0 << 16 |
|
|
CARMINE_DFLT_IP_DCTL_STATES;
|
|
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_RSV0_STATES,
|
|
flags);
|
|
|
|
/* Executes DLL reset */
|
|
if (CARMINE_DCTL_DLL_RESET) {
|
|
for (loops = 0; loops < CARMINE_DCTL_INIT_WAIT_LIMIT; loops++) {
|
|
|
|
ret = c_get_hw_reg(hw, CARMINE_DCTL_REG +
|
|
CARMINE_DCTL_REG_RSV0_STATES);
|
|
ret &= CARMINE_DCTL_REG_STATES_MASK;
|
|
if (!ret)
|
|
break;
|
|
|
|
mdelay(CARMINE_DCTL_INIT_WAIT_INTERVAL);
|
|
}
|
|
|
|
if (loops >= CARMINE_DCTL_INIT_WAIT_LIMIT) {
|
|
printk(KERN_ERR "DRAM init failed\n");
|
|
return -EIO;
|
|
}
|
|
}
|
|
|
|
flags = CARMINE_DFLT_IP_DCTL_MODE_AFT_RST << 16 |
|
|
CARMINE_DFLT_IP_DCTL_ADD;
|
|
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_MODE_ADD, flags);
|
|
|
|
flags = CARMINE_DFLT_IP_DCTL_RESERVE0 << 16 |
|
|
CARMINE_DFLT_IP_DCTL_STATES_AFT_RST;
|
|
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_RSV0_STATES,
|
|
flags);
|
|
|
|
/* Initialize the write back register */
|
|
c_set_hw_reg(hw, CARMINE_WB_REG + CARMINE_WB_REG_WBM,
|
|
CARMINE_WB_REG_WBM_DEFAULT);
|
|
|
|
/* Initialize the Kottos registers */
|
|
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_VRINTM, 0);
|
|
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_VRERRM, 0);
|
|
|
|
/* Set DC offsets */
|
|
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_PX, 0);
|
|
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_PY, 0);
|
|
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_LX, 0);
|
|
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_LY, 0);
|
|
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_TX, 0);
|
|
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_TY, 0);
|
|
return 0;
|
|
}
|
|
|
|
static struct fb_ops carminefb_ops = {
|
|
.owner = THIS_MODULE,
|
|
.fb_fillrect = cfb_fillrect,
|
|
.fb_copyarea = cfb_copyarea,
|
|
.fb_imageblit = cfb_imageblit,
|
|
|
|
.fb_check_var = carmine_check_var,
|
|
.fb_set_par = carmine_set_par,
|
|
.fb_setcolreg = carmine_setcolreg,
|
|
};
|
|
|
|
static int __devinit alloc_carmine_fb(void __iomem *regs, void __iomem *smem_base,
|
|
int smem_offset, struct device *device, struct fb_info **rinfo)
|
|
{
|
|
int ret;
|
|
struct fb_info *info;
|
|
struct carmine_fb *par;
|
|
|
|
info = framebuffer_alloc(sizeof *par, device);
|
|
if (!info)
|
|
return -ENOMEM;
|
|
|
|
par = info->par;
|
|
par->display_reg = regs;
|
|
par->smem_offset = smem_offset;
|
|
|
|
info->screen_base = smem_base + smem_offset;
|
|
info->screen_size = CARMINE_DISPLAY_MEM;
|
|
info->fbops = &carminefb_ops;
|
|
|
|
info->fix = carminefb_fix;
|
|
info->pseudo_palette = par->pseudo_palette;
|
|
info->flags = FBINFO_DEFAULT;
|
|
|
|
ret = fb_alloc_cmap(&info->cmap, 256, 1);
|
|
if (ret < 0)
|
|
goto err_free_fb;
|
|
|
|
if (fb_mode > ARRAY_SIZE(carmine_modedb))
|
|
fb_mode = CARMINEFB_DEFAULT_VIDEO_MODE;
|
|
|
|
par->cur_mode = par->new_mode = ~0;
|
|
|
|
ret = fb_find_mode(&info->var, info, fb_mode_str, carmine_modedb,
|
|
ARRAY_SIZE(carmine_modedb),
|
|
&carmine_modedb[fb_mode], 32);
|
|
if (!ret || ret == 4) {
|
|
ret = -EINVAL;
|
|
goto err_dealloc_cmap;
|
|
}
|
|
|
|
fb_videomode_to_modelist(carmine_modedb, ARRAY_SIZE(carmine_modedb),
|
|
&info->modelist);
|
|
|
|
ret = register_framebuffer(info);
|
|
if (ret < 0)
|
|
goto err_dealloc_cmap;
|
|
|
|
printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
|
|
info->fix.id);
|
|
|
|
*rinfo = info;
|
|
return 0;
|
|
|
|
err_dealloc_cmap:
|
|
fb_dealloc_cmap(&info->cmap);
|
|
err_free_fb:
|
|
framebuffer_release(info);
|
|
return ret;
|
|
}
|
|
|
|
static void cleanup_fb_device(struct fb_info *info)
|
|
{
|
|
if (info) {
|
|
unregister_framebuffer(info);
|
|
fb_dealloc_cmap(&info->cmap);
|
|
framebuffer_release(info);
|
|
}
|
|
}
|
|
|
|
static int __devinit carminefb_probe(struct pci_dev *dev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
struct carmine_hw *hw;
|
|
struct device *device = &dev->dev;
|
|
struct fb_info *info;
|
|
int ret;
|
|
|
|
ret = pci_enable_device(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = -ENOMEM;
|
|
hw = kzalloc(sizeof *hw, GFP_KERNEL);
|
|
if (!hw)
|
|
goto err_enable_pci;
|
|
|
|
carminefb_fix.mmio_start = pci_resource_start(dev, CARMINE_CONFIG_BAR);
|
|
carminefb_fix.mmio_len = pci_resource_len(dev, CARMINE_CONFIG_BAR);
|
|
|
|
if (!request_mem_region(carminefb_fix.mmio_start,
|
|
carminefb_fix.mmio_len,
|
|
"carminefb regbase")) {
|
|
printk(KERN_ERR "carminefb: Can't reserve regbase.\n");
|
|
ret = -EBUSY;
|
|
goto err_free_hw;
|
|
}
|
|
hw->v_regs = ioremap_nocache(carminefb_fix.mmio_start,
|
|
carminefb_fix.mmio_len);
|
|
if (!hw->v_regs) {
|
|
printk(KERN_ERR "carminefb: Can't remap %s register.\n",
|
|
carminefb_fix.id);
|
|
goto err_free_reg_mmio;
|
|
}
|
|
|
|
carminefb_fix.smem_start = pci_resource_start(dev, CARMINE_MEMORY_BAR);
|
|
carminefb_fix.smem_len = pci_resource_len(dev, CARMINE_MEMORY_BAR);
|
|
|
|
/* The memory area tends to be very large (256 MiB). Remap only what
|
|
* is required for that largest resolution to avoid remaps at run
|
|
* time
|
|
*/
|
|
if (carminefb_fix.smem_len > CARMINE_TOTAL_DIPLAY_MEM)
|
|
carminefb_fix.smem_len = CARMINE_TOTAL_DIPLAY_MEM;
|
|
|
|
else if (carminefb_fix.smem_len < CARMINE_TOTAL_DIPLAY_MEM) {
|
|
printk(KERN_ERR "carminefb: Memory bar is only %d bytes, %d "
|
|
"are required.", carminefb_fix.smem_len,
|
|
CARMINE_TOTAL_DIPLAY_MEM);
|
|
goto err_free_reg_mmio;
|
|
}
|
|
|
|
if (!request_mem_region(carminefb_fix.smem_start,
|
|
carminefb_fix.smem_len, "carminefb smem")) {
|
|
printk(KERN_ERR "carminefb: Can't reserve smem.\n");
|
|
goto err_unmap_vregs;
|
|
}
|
|
|
|
hw->screen_mem = ioremap_nocache(carminefb_fix.smem_start,
|
|
carminefb_fix.smem_len);
|
|
if (!hw->screen_mem) {
|
|
printk(KERN_ERR "carmine: Can't ioremap smem area.\n");
|
|
release_mem_region(carminefb_fix.smem_start,
|
|
carminefb_fix.smem_len);
|
|
goto err_reg_smem;
|
|
}
|
|
|
|
ret = init_hardware(hw);
|
|
if (ret)
|
|
goto err_unmap_screen;
|
|
|
|
info = NULL;
|
|
if (fb_displays & CARMINE_USE_DISPLAY0) {
|
|
ret = alloc_carmine_fb(hw->v_regs + CARMINE_DISP0_REG,
|
|
hw->screen_mem, CARMINE_DISPLAY_MEM * 0,
|
|
device, &info);
|
|
if (ret)
|
|
goto err_deinit_hw;
|
|
}
|
|
|
|
hw->fb[0] = info;
|
|
|
|
info = NULL;
|
|
if (fb_displays & CARMINE_USE_DISPLAY1) {
|
|
ret = alloc_carmine_fb(hw->v_regs + CARMINE_DISP1_REG,
|
|
hw->screen_mem, CARMINE_DISPLAY_MEM * 1,
|
|
device, &info);
|
|
if (ret)
|
|
goto err_cleanup_fb0;
|
|
}
|
|
|
|
hw->fb[1] = info;
|
|
info = NULL;
|
|
|
|
pci_set_drvdata(dev, hw);
|
|
return 0;
|
|
|
|
err_cleanup_fb0:
|
|
cleanup_fb_device(hw->fb[0]);
|
|
err_deinit_hw:
|
|
/* disable clock, etc */
|
|
c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_CLOCK_ENABLE, 0);
|
|
err_unmap_screen:
|
|
iounmap(hw->screen_mem);
|
|
err_reg_smem:
|
|
release_mem_region(carminefb_fix.mmio_start, carminefb_fix.mmio_len);
|
|
err_unmap_vregs:
|
|
iounmap(hw->v_regs);
|
|
err_free_reg_mmio:
|
|
release_mem_region(carminefb_fix.mmio_start, carminefb_fix.mmio_len);
|
|
err_free_hw:
|
|
kfree(hw);
|
|
err_enable_pci:
|
|
pci_disable_device(dev);
|
|
return ret;
|
|
}
|
|
|
|
static void __devexit carminefb_remove(struct pci_dev *dev)
|
|
{
|
|
struct carmine_hw *hw = pci_get_drvdata(dev);
|
|
struct fb_fix_screeninfo fix;
|
|
int i;
|
|
|
|
/* in case we use only fb1 and not fb1 */
|
|
if (hw->fb[0])
|
|
fix = hw->fb[0]->fix;
|
|
else
|
|
fix = hw->fb[1]->fix;
|
|
|
|
/* deactivate display(s) and switch clocks */
|
|
c_set_hw_reg(hw, CARMINE_DISP0_REG + CARMINE_DISP_REG_DCM1, 0);
|
|
c_set_hw_reg(hw, CARMINE_DISP1_REG + CARMINE_DISP_REG_DCM1, 0);
|
|
c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_CLOCK_ENABLE, 0);
|
|
|
|
for (i = 0; i < MAX_DISPLAY; i++)
|
|
cleanup_fb_device(hw->fb[i]);
|
|
|
|
iounmap(hw->screen_mem);
|
|
release_mem_region(fix.smem_start, fix.smem_len);
|
|
iounmap(hw->v_regs);
|
|
release_mem_region(fix.mmio_start, fix.mmio_len);
|
|
|
|
pci_set_drvdata(dev, NULL);
|
|
pci_disable_device(dev);
|
|
kfree(hw);
|
|
}
|
|
|
|
#define PCI_VENDOR_ID_FUJITU_LIMITED 0x10cf
|
|
static struct pci_device_id carmine_devices[] __devinitdata = {
|
|
{
|
|
PCI_DEVICE(PCI_VENDOR_ID_FUJITU_LIMITED, 0x202b)},
|
|
{0, 0, 0, 0, 0, 0, 0}
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, carmine_devices);
|
|
|
|
static struct pci_driver carmine_pci_driver = {
|
|
.name = "carminefb",
|
|
.id_table = carmine_devices,
|
|
.probe = carminefb_probe,
|
|
.remove = __devexit_p(carminefb_remove),
|
|
};
|
|
|
|
static int __init carminefb_init(void)
|
|
{
|
|
if (!(fb_displays &
|
|
(CARMINE_USE_DISPLAY0 | CARMINE_USE_DISPLAY1))) {
|
|
printk(KERN_ERR "If you disable both displays than you don't "
|
|
"need the driver at all\n");
|
|
return -EINVAL;
|
|
}
|
|
return pci_register_driver(&carmine_pci_driver);
|
|
}
|
|
module_init(carminefb_init);
|
|
|
|
static void __exit carminefb_cleanup(void)
|
|
{
|
|
pci_unregister_driver(&carmine_pci_driver);
|
|
}
|
|
module_exit(carminefb_cleanup);
|
|
|
|
MODULE_AUTHOR("Sebastian Siewior <bigeasy@linutronix.de>");
|
|
MODULE_DESCRIPTION("Framebuffer driver for Fujitsu Carmine based devices");
|
|
MODULE_LICENSE("GPL v2");
|