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![Saeed Bishara](/assets/img/avatar_default.png)
Some controllers (KW, Dove) limits the TX IP/layer4 checksum offloading to a max size. Signed-off-by: Saeed Bishara <saeed@marvell.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: David S. Miller <davem@davemloft.net>
83 lines
1.8 KiB
C
83 lines
1.8 KiB
C
/*
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* MV-643XX ethernet platform device data definition file.
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*/
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#ifndef __LINUX_MV643XX_ETH_H
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#define __LINUX_MV643XX_ETH_H
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#include <linux/mbus.h>
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#define MV643XX_ETH_SHARED_NAME "mv643xx_eth"
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#define MV643XX_ETH_NAME "mv643xx_eth_port"
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#define MV643XX_ETH_SHARED_REGS 0x2000
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#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
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#define MV643XX_ETH_BAR_4 0x2220
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#define MV643XX_ETH_SIZE_REG_4 0x2224
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#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
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struct mv643xx_eth_shared_platform_data {
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struct mbus_dram_target_info *dram;
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struct platform_device *shared_smi;
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unsigned int t_clk;
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/*
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* Max packet size for Tx IP/Layer 4 checksum, when set to 0, default
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* limit of 9KiB will be used.
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*/
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int tx_csum_limit;
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};
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#define MV643XX_ETH_PHY_ADDR_DEFAULT 0
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#define MV643XX_ETH_PHY_ADDR(x) (0x80 | (x))
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#define MV643XX_ETH_PHY_NONE 0xff
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struct mv643xx_eth_platform_data {
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/*
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* Pointer back to our parent instance, and our port number.
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*/
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struct platform_device *shared;
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int port_number;
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/*
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* Whether a PHY is present, and if yes, at which address.
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*/
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int phy_addr;
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/*
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* Use this MAC address if it is valid, overriding the
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* address that is already in the hardware.
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*/
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u8 mac_addr[6];
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/*
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* If speed is 0, autonegotiation is enabled.
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* Valid values for speed: 0, SPEED_10, SPEED_100, SPEED_1000.
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* Valid values for duplex: DUPLEX_HALF, DUPLEX_FULL.
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*/
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int speed;
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int duplex;
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/*
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* How many RX/TX queues to use.
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*/
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int rx_queue_count;
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int tx_queue_count;
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/*
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* Override default RX/TX queue sizes if nonzero.
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*/
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int rx_queue_size;
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int tx_queue_size;
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/*
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* Use on-chip SRAM for RX/TX descriptors if size is nonzero
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* and sufficient to contain all descriptors for the requested
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* ring sizes.
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*/
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unsigned long rx_sram_addr;
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int rx_sram_size;
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unsigned long tx_sram_addr;
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int tx_sram_size;
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};
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#endif
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