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![Tom 'spot' Callaway](/assets/img/avatar_default.png)
Minor cleanups for sparc specific drivers (sunbmac, sunqe, sunlance, sunhme, esp) so that they have a full module version definition that is consistent with other upstream drivers. Signed-off-by: Tom 'spot' Callaway <tcallawa@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1052 lines
27 KiB
C
1052 lines
27 KiB
C
/* $Id: sunqe.c,v 1.55 2002/01/15 06:48:55 davem Exp $
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* sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver.
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* Once again I am out to prove that every ethernet
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* controller out there can be most efficiently programmed
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* if you make it look like a LANCE.
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*
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* Copyright (C) 1996, 1999, 2003 David S. Miller (davem@redhat.com)
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/fcntl.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/in.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/crc32.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/ethtool.h>
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#include <linux/bitops.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/dma.h>
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#include <asm/byteorder.h>
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#include <asm/idprom.h>
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#include <asm/sbus.h>
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#include <asm/openprom.h>
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#include <asm/oplib.h>
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#include <asm/auxio.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include "sunqe.h"
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#define DRV_NAME "sunqe"
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#define DRV_VERSION "3.0"
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#define DRV_RELDATE "8/24/03"
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#define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
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static char version[] =
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DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
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MODULE_VERSION(DRV_VERSION);
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MODULE_AUTHOR(DRV_AUTHOR);
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MODULE_DESCRIPTION("Sun QuadEthernet 10baseT SBUS card driver");
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MODULE_LICENSE("GPL");
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static struct sunqec *root_qec_dev;
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static void qe_set_multicast(struct net_device *dev);
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#define QEC_RESET_TRIES 200
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static inline int qec_global_reset(void __iomem *gregs)
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{
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int tries = QEC_RESET_TRIES;
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sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
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while (--tries) {
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u32 tmp = sbus_readl(gregs + GLOB_CTRL);
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if (tmp & GLOB_CTRL_RESET) {
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udelay(20);
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continue;
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}
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break;
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}
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if (tries)
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return 0;
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printk(KERN_ERR "QuadEther: AIEEE cannot reset the QEC!\n");
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return -1;
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}
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#define MACE_RESET_RETRIES 200
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#define QE_RESET_RETRIES 200
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static inline int qe_stop(struct sunqe *qep)
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{
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void __iomem *cregs = qep->qcregs;
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void __iomem *mregs = qep->mregs;
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int tries;
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/* Reset the MACE, then the QEC channel. */
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sbus_writeb(MREGS_BCONFIG_RESET, mregs + MREGS_BCONFIG);
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tries = MACE_RESET_RETRIES;
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while (--tries) {
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u8 tmp = sbus_readb(mregs + MREGS_BCONFIG);
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if (tmp & MREGS_BCONFIG_RESET) {
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udelay(20);
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continue;
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}
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break;
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}
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if (!tries) {
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printk(KERN_ERR "QuadEther: AIEEE cannot reset the MACE!\n");
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return -1;
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}
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sbus_writel(CREG_CTRL_RESET, cregs + CREG_CTRL);
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tries = QE_RESET_RETRIES;
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while (--tries) {
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u32 tmp = sbus_readl(cregs + CREG_CTRL);
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if (tmp & CREG_CTRL_RESET) {
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udelay(20);
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continue;
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}
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break;
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}
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if (!tries) {
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printk(KERN_ERR "QuadEther: Cannot reset QE channel!\n");
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return -1;
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}
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return 0;
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}
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static void qe_init_rings(struct sunqe *qep)
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{
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struct qe_init_block *qb = qep->qe_block;
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struct sunqe_buffers *qbufs = qep->buffers;
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__u32 qbufs_dvma = qep->buffers_dvma;
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int i;
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qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0;
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memset(qb, 0, sizeof(struct qe_init_block));
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memset(qbufs, 0, sizeof(struct sunqe_buffers));
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for (i = 0; i < RX_RING_SIZE; i++) {
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qb->qe_rxd[i].rx_addr = qbufs_dvma + qebuf_offset(rx_buf, i);
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qb->qe_rxd[i].rx_flags =
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(RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
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}
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}
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static int qe_init(struct sunqe *qep, int from_irq)
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{
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struct sunqec *qecp = qep->parent;
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void __iomem *cregs = qep->qcregs;
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void __iomem *mregs = qep->mregs;
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void __iomem *gregs = qecp->gregs;
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unsigned char *e = &qep->dev->dev_addr[0];
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u32 tmp;
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int i;
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/* Shut it up. */
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if (qe_stop(qep))
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return -EAGAIN;
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/* Setup initial rx/tx init block pointers. */
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sbus_writel(qep->qblock_dvma + qib_offset(qe_rxd, 0), cregs + CREG_RXDS);
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sbus_writel(qep->qblock_dvma + qib_offset(qe_txd, 0), cregs + CREG_TXDS);
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/* Enable/mask the various irq's. */
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sbus_writel(0, cregs + CREG_RIMASK);
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sbus_writel(1, cregs + CREG_TIMASK);
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sbus_writel(0, cregs + CREG_QMASK);
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sbus_writel(CREG_MMASK_RXCOLL, cregs + CREG_MMASK);
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/* Setup the FIFO pointers into QEC local memory. */
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tmp = qep->channel * sbus_readl(gregs + GLOB_MSIZE);
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sbus_writel(tmp, cregs + CREG_RXRBUFPTR);
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sbus_writel(tmp, cregs + CREG_RXWBUFPTR);
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tmp = sbus_readl(cregs + CREG_RXRBUFPTR) +
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sbus_readl(gregs + GLOB_RSIZE);
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sbus_writel(tmp, cregs + CREG_TXRBUFPTR);
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sbus_writel(tmp, cregs + CREG_TXWBUFPTR);
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/* Clear the channel collision counter. */
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sbus_writel(0, cregs + CREG_CCNT);
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/* For 10baseT, inter frame space nor throttle seems to be necessary. */
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sbus_writel(0, cregs + CREG_PIPG);
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/* Now dork with the AMD MACE. */
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sbus_writeb(MREGS_PHYCONFIG_AUTO, mregs + MREGS_PHYCONFIG);
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sbus_writeb(MREGS_TXFCNTL_AUTOPAD, mregs + MREGS_TXFCNTL);
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sbus_writeb(0, mregs + MREGS_RXFCNTL);
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/* The QEC dma's the rx'd packets from local memory out to main memory,
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* and therefore it interrupts when the packet reception is "complete".
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* So don't listen for the MACE talking about it.
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*/
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sbus_writeb(MREGS_IMASK_COLL | MREGS_IMASK_RXIRQ, mregs + MREGS_IMASK);
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sbus_writeb(MREGS_BCONFIG_BSWAP | MREGS_BCONFIG_64TS, mregs + MREGS_BCONFIG);
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sbus_writeb((MREGS_FCONFIG_TXF16 | MREGS_FCONFIG_RXF32 |
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MREGS_FCONFIG_RFWU | MREGS_FCONFIG_TFWU),
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mregs + MREGS_FCONFIG);
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/* Only usable interface on QuadEther is twisted pair. */
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sbus_writeb(MREGS_PLSCONFIG_TP, mregs + MREGS_PLSCONFIG);
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/* Tell MACE we are changing the ether address. */
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sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_PARESET,
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mregs + MREGS_IACONFIG);
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while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
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barrier();
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sbus_writeb(e[0], mregs + MREGS_ETHADDR);
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sbus_writeb(e[1], mregs + MREGS_ETHADDR);
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sbus_writeb(e[2], mregs + MREGS_ETHADDR);
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sbus_writeb(e[3], mregs + MREGS_ETHADDR);
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sbus_writeb(e[4], mregs + MREGS_ETHADDR);
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sbus_writeb(e[5], mregs + MREGS_ETHADDR);
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/* Clear out the address filter. */
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sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
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mregs + MREGS_IACONFIG);
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while ((sbus_readb(mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
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barrier();
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for (i = 0; i < 8; i++)
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sbus_writeb(0, mregs + MREGS_FILTER);
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/* Address changes are now complete. */
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sbus_writeb(0, mregs + MREGS_IACONFIG);
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qe_init_rings(qep);
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/* Wait a little bit for the link to come up... */
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mdelay(5);
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if (!(sbus_readb(mregs + MREGS_PHYCONFIG) & MREGS_PHYCONFIG_LTESTDIS)) {
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int tries = 50;
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while (tries--) {
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u8 tmp;
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mdelay(5);
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barrier();
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tmp = sbus_readb(mregs + MREGS_PHYCONFIG);
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if ((tmp & MREGS_PHYCONFIG_LSTAT) != 0)
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break;
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}
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if (tries == 0)
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printk(KERN_NOTICE "%s: Warning, link state is down.\n", qep->dev->name);
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}
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/* Missed packet counter is cleared on a read. */
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sbus_readb(mregs + MREGS_MPCNT);
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/* Reload multicast information, this will enable the receiver
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* and transmitter.
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*/
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qe_set_multicast(qep->dev);
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/* QEC should now start to show interrupts. */
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return 0;
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}
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/* Grrr, certain error conditions completely lock up the AMD MACE,
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* so when we get these we _must_ reset the chip.
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*/
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static int qe_is_bolixed(struct sunqe *qep, u32 qe_status)
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{
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struct net_device *dev = qep->dev;
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int mace_hwbug_workaround = 0;
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if (qe_status & CREG_STAT_EDEFER) {
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printk(KERN_ERR "%s: Excessive transmit defers.\n", dev->name);
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qep->net_stats.tx_errors++;
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}
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if (qe_status & CREG_STAT_CLOSS) {
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printk(KERN_ERR "%s: Carrier lost, link down?\n", dev->name);
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qep->net_stats.tx_errors++;
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qep->net_stats.tx_carrier_errors++;
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}
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if (qe_status & CREG_STAT_ERETRIES) {
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printk(KERN_ERR "%s: Excessive transmit retries (more than 16).\n", dev->name);
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qep->net_stats.tx_errors++;
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mace_hwbug_workaround = 1;
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}
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if (qe_status & CREG_STAT_LCOLL) {
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printk(KERN_ERR "%s: Late transmit collision.\n", dev->name);
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qep->net_stats.tx_errors++;
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qep->net_stats.collisions++;
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mace_hwbug_workaround = 1;
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}
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if (qe_status & CREG_STAT_FUFLOW) {
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printk(KERN_ERR "%s: Transmit fifo underflow, driver bug.\n", dev->name);
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qep->net_stats.tx_errors++;
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mace_hwbug_workaround = 1;
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}
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if (qe_status & CREG_STAT_JERROR) {
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printk(KERN_ERR "%s: Jabber error.\n", dev->name);
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}
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if (qe_status & CREG_STAT_BERROR) {
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printk(KERN_ERR "%s: Babble error.\n", dev->name);
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}
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if (qe_status & CREG_STAT_CCOFLOW) {
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qep->net_stats.tx_errors += 256;
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qep->net_stats.collisions += 256;
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}
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if (qe_status & CREG_STAT_TXDERROR) {
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printk(KERN_ERR "%s: Transmit descriptor is bogus, driver bug.\n", dev->name);
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qep->net_stats.tx_errors++;
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qep->net_stats.tx_aborted_errors++;
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mace_hwbug_workaround = 1;
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}
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if (qe_status & CREG_STAT_TXLERR) {
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printk(KERN_ERR "%s: Transmit late error.\n", dev->name);
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qep->net_stats.tx_errors++;
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mace_hwbug_workaround = 1;
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}
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if (qe_status & CREG_STAT_TXPERR) {
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printk(KERN_ERR "%s: Transmit DMA parity error.\n", dev->name);
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qep->net_stats.tx_errors++;
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qep->net_stats.tx_aborted_errors++;
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mace_hwbug_workaround = 1;
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}
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if (qe_status & CREG_STAT_TXSERR) {
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printk(KERN_ERR "%s: Transmit DMA sbus error ack.\n", dev->name);
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qep->net_stats.tx_errors++;
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qep->net_stats.tx_aborted_errors++;
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mace_hwbug_workaround = 1;
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}
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if (qe_status & CREG_STAT_RCCOFLOW) {
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qep->net_stats.rx_errors += 256;
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qep->net_stats.collisions += 256;
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}
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if (qe_status & CREG_STAT_RUOFLOW) {
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qep->net_stats.rx_errors += 256;
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qep->net_stats.rx_over_errors += 256;
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}
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if (qe_status & CREG_STAT_MCOFLOW) {
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qep->net_stats.rx_errors += 256;
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qep->net_stats.rx_missed_errors += 256;
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}
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if (qe_status & CREG_STAT_RXFOFLOW) {
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printk(KERN_ERR "%s: Receive fifo overflow.\n", dev->name);
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qep->net_stats.rx_errors++;
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qep->net_stats.rx_over_errors++;
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}
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if (qe_status & CREG_STAT_RLCOLL) {
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printk(KERN_ERR "%s: Late receive collision.\n", dev->name);
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qep->net_stats.rx_errors++;
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qep->net_stats.collisions++;
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}
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if (qe_status & CREG_STAT_FCOFLOW) {
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qep->net_stats.rx_errors += 256;
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qep->net_stats.rx_frame_errors += 256;
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}
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if (qe_status & CREG_STAT_CECOFLOW) {
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qep->net_stats.rx_errors += 256;
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qep->net_stats.rx_crc_errors += 256;
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}
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if (qe_status & CREG_STAT_RXDROP) {
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printk(KERN_ERR "%s: Receive packet dropped.\n", dev->name);
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qep->net_stats.rx_errors++;
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qep->net_stats.rx_dropped++;
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qep->net_stats.rx_missed_errors++;
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}
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if (qe_status & CREG_STAT_RXSMALL) {
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printk(KERN_ERR "%s: Receive buffer too small, driver bug.\n", dev->name);
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qep->net_stats.rx_errors++;
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qep->net_stats.rx_length_errors++;
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}
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if (qe_status & CREG_STAT_RXLERR) {
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printk(KERN_ERR "%s: Receive late error.\n", dev->name);
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qep->net_stats.rx_errors++;
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mace_hwbug_workaround = 1;
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}
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if (qe_status & CREG_STAT_RXPERR) {
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printk(KERN_ERR "%s: Receive DMA parity error.\n", dev->name);
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qep->net_stats.rx_errors++;
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qep->net_stats.rx_missed_errors++;
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mace_hwbug_workaround = 1;
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}
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if (qe_status & CREG_STAT_RXSERR) {
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printk(KERN_ERR "%s: Receive DMA sbus error ack.\n", dev->name);
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qep->net_stats.rx_errors++;
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qep->net_stats.rx_missed_errors++;
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mace_hwbug_workaround = 1;
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}
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if (mace_hwbug_workaround)
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qe_init(qep, 1);
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return mace_hwbug_workaround;
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}
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/* Per-QE receive interrupt service routine. Just like on the happy meal
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* we receive directly into skb's with a small packet copy water mark.
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*/
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static void qe_rx(struct sunqe *qep)
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{
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struct qe_rxd *rxbase = &qep->qe_block->qe_rxd[0];
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struct qe_rxd *this;
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struct sunqe_buffers *qbufs = qep->buffers;
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__u32 qbufs_dvma = qep->buffers_dvma;
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int elem = qep->rx_new, drops = 0;
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u32 flags;
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this = &rxbase[elem];
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while (!((flags = this->rx_flags) & RXD_OWN)) {
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struct sk_buff *skb;
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unsigned char *this_qbuf =
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&qbufs->rx_buf[elem & (RX_RING_SIZE - 1)][0];
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__u32 this_qbuf_dvma = qbufs_dvma +
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qebuf_offset(rx_buf, (elem & (RX_RING_SIZE - 1)));
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struct qe_rxd *end_rxd =
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&rxbase[(elem+RX_RING_SIZE)&(RX_RING_MAXSIZE-1)];
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int len = (flags & RXD_LENGTH) - 4; /* QE adds ether FCS size to len */
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/* Check for errors. */
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if (len < ETH_ZLEN) {
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qep->net_stats.rx_errors++;
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qep->net_stats.rx_length_errors++;
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qep->net_stats.rx_dropped++;
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} else {
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skb = dev_alloc_skb(len + 2);
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if (skb == NULL) {
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drops++;
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qep->net_stats.rx_dropped++;
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} else {
|
|
skb->dev = qep->dev;
|
|
skb_reserve(skb, 2);
|
|
skb_put(skb, len);
|
|
eth_copy_and_sum(skb, (unsigned char *) this_qbuf,
|
|
len, 0);
|
|
skb->protocol = eth_type_trans(skb, qep->dev);
|
|
netif_rx(skb);
|
|
qep->dev->last_rx = jiffies;
|
|
qep->net_stats.rx_packets++;
|
|
qep->net_stats.rx_bytes += len;
|
|
}
|
|
}
|
|
end_rxd->rx_addr = this_qbuf_dvma;
|
|
end_rxd->rx_flags = (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
|
|
|
|
elem = NEXT_RX(elem);
|
|
this = &rxbase[elem];
|
|
}
|
|
qep->rx_new = elem;
|
|
if (drops)
|
|
printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", qep->dev->name);
|
|
}
|
|
|
|
static void qe_tx_reclaim(struct sunqe *qep);
|
|
|
|
/* Interrupts for all QE's get filtered out via the QEC master controller,
|
|
* so we just run through each qe and check to see who is signaling
|
|
* and thus needs to be serviced.
|
|
*/
|
|
static irqreturn_t qec_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
struct sunqec *qecp = (struct sunqec *) dev_id;
|
|
u32 qec_status;
|
|
int channel = 0;
|
|
|
|
/* Latch the status now. */
|
|
qec_status = sbus_readl(qecp->gregs + GLOB_STAT);
|
|
while (channel < 4) {
|
|
if (qec_status & 0xf) {
|
|
struct sunqe *qep = qecp->qes[channel];
|
|
u32 qe_status;
|
|
|
|
qe_status = sbus_readl(qep->qcregs + CREG_STAT);
|
|
if (qe_status & CREG_STAT_ERRORS) {
|
|
if (qe_is_bolixed(qep, qe_status))
|
|
goto next;
|
|
}
|
|
if (qe_status & CREG_STAT_RXIRQ)
|
|
qe_rx(qep);
|
|
if (netif_queue_stopped(qep->dev) &&
|
|
(qe_status & CREG_STAT_TXIRQ)) {
|
|
spin_lock(&qep->lock);
|
|
qe_tx_reclaim(qep);
|
|
if (TX_BUFFS_AVAIL(qep) > 0) {
|
|
/* Wake net queue and return to
|
|
* lazy tx reclaim.
|
|
*/
|
|
netif_wake_queue(qep->dev);
|
|
sbus_writel(1, qep->qcregs + CREG_TIMASK);
|
|
}
|
|
spin_unlock(&qep->lock);
|
|
}
|
|
next:
|
|
;
|
|
}
|
|
qec_status >>= 4;
|
|
channel++;
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int qe_open(struct net_device *dev)
|
|
{
|
|
struct sunqe *qep = (struct sunqe *) dev->priv;
|
|
|
|
qep->mconfig = (MREGS_MCONFIG_TXENAB |
|
|
MREGS_MCONFIG_RXENAB |
|
|
MREGS_MCONFIG_MBAENAB);
|
|
return qe_init(qep, 0);
|
|
}
|
|
|
|
static int qe_close(struct net_device *dev)
|
|
{
|
|
struct sunqe *qep = (struct sunqe *) dev->priv;
|
|
|
|
qe_stop(qep);
|
|
return 0;
|
|
}
|
|
|
|
/* Reclaim TX'd frames from the ring. This must always run under
|
|
* the IRQ protected qep->lock.
|
|
*/
|
|
static void qe_tx_reclaim(struct sunqe *qep)
|
|
{
|
|
struct qe_txd *txbase = &qep->qe_block->qe_txd[0];
|
|
int elem = qep->tx_old;
|
|
|
|
while (elem != qep->tx_new) {
|
|
u32 flags = txbase[elem].tx_flags;
|
|
|
|
if (flags & TXD_OWN)
|
|
break;
|
|
elem = NEXT_TX(elem);
|
|
}
|
|
qep->tx_old = elem;
|
|
}
|
|
|
|
static void qe_tx_timeout(struct net_device *dev)
|
|
{
|
|
struct sunqe *qep = (struct sunqe *) dev->priv;
|
|
int tx_full;
|
|
|
|
spin_lock_irq(&qep->lock);
|
|
|
|
/* Try to reclaim, if that frees up some tx
|
|
* entries, we're fine.
|
|
*/
|
|
qe_tx_reclaim(qep);
|
|
tx_full = TX_BUFFS_AVAIL(qep) <= 0;
|
|
|
|
spin_unlock_irq(&qep->lock);
|
|
|
|
if (! tx_full)
|
|
goto out;
|
|
|
|
printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
|
|
qe_init(qep, 1);
|
|
|
|
out:
|
|
netif_wake_queue(dev);
|
|
}
|
|
|
|
/* Get a packet queued to go onto the wire. */
|
|
static int qe_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
struct sunqe *qep = (struct sunqe *) dev->priv;
|
|
struct sunqe_buffers *qbufs = qep->buffers;
|
|
__u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma;
|
|
unsigned char *txbuf;
|
|
int len, entry;
|
|
|
|
spin_lock_irq(&qep->lock);
|
|
|
|
qe_tx_reclaim(qep);
|
|
|
|
len = skb->len;
|
|
entry = qep->tx_new;
|
|
|
|
txbuf = &qbufs->tx_buf[entry & (TX_RING_SIZE - 1)][0];
|
|
txbuf_dvma = qbufs_dvma +
|
|
qebuf_offset(tx_buf, (entry & (TX_RING_SIZE - 1)));
|
|
|
|
/* Avoid a race... */
|
|
qep->qe_block->qe_txd[entry].tx_flags = TXD_UPDATE;
|
|
|
|
memcpy(txbuf, skb->data, len);
|
|
|
|
qep->qe_block->qe_txd[entry].tx_addr = txbuf_dvma;
|
|
qep->qe_block->qe_txd[entry].tx_flags =
|
|
(TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
|
|
qep->tx_new = NEXT_TX(entry);
|
|
|
|
/* Get it going. */
|
|
dev->trans_start = jiffies;
|
|
sbus_writel(CREG_CTRL_TWAKEUP, qep->qcregs + CREG_CTRL);
|
|
|
|
qep->net_stats.tx_packets++;
|
|
qep->net_stats.tx_bytes += len;
|
|
|
|
if (TX_BUFFS_AVAIL(qep) <= 0) {
|
|
/* Halt the net queue and enable tx interrupts.
|
|
* When the tx queue empties the tx irq handler
|
|
* will wake up the queue and return us back to
|
|
* the lazy tx reclaim scheme.
|
|
*/
|
|
netif_stop_queue(dev);
|
|
sbus_writel(0, qep->qcregs + CREG_TIMASK);
|
|
}
|
|
spin_unlock_irq(&qep->lock);
|
|
|
|
dev_kfree_skb(skb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct net_device_stats *qe_get_stats(struct net_device *dev)
|
|
{
|
|
struct sunqe *qep = (struct sunqe *) dev->priv;
|
|
|
|
return &qep->net_stats;
|
|
}
|
|
|
|
static void qe_set_multicast(struct net_device *dev)
|
|
{
|
|
struct sunqe *qep = (struct sunqe *) dev->priv;
|
|
struct dev_mc_list *dmi = dev->mc_list;
|
|
u8 new_mconfig = qep->mconfig;
|
|
char *addrs;
|
|
int i;
|
|
u32 crc;
|
|
|
|
/* Lock out others. */
|
|
netif_stop_queue(dev);
|
|
|
|
if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
|
|
sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
|
|
qep->mregs + MREGS_IACONFIG);
|
|
while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
|
|
barrier();
|
|
for (i = 0; i < 8; i++)
|
|
sbus_writeb(0xff, qep->mregs + MREGS_FILTER);
|
|
sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
|
|
} else if (dev->flags & IFF_PROMISC) {
|
|
new_mconfig |= MREGS_MCONFIG_PROMISC;
|
|
} else {
|
|
u16 hash_table[4];
|
|
u8 *hbytes = (unsigned char *) &hash_table[0];
|
|
|
|
for (i = 0; i < 4; i++)
|
|
hash_table[i] = 0;
|
|
|
|
for (i = 0; i < dev->mc_count; i++) {
|
|
addrs = dmi->dmi_addr;
|
|
dmi = dmi->next;
|
|
|
|
if (!(*addrs & 1))
|
|
continue;
|
|
crc = ether_crc_le(6, addrs);
|
|
crc >>= 26;
|
|
hash_table[crc >> 4] |= 1 << (crc & 0xf);
|
|
}
|
|
/* Program the qe with the new filter value. */
|
|
sbus_writeb(MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET,
|
|
qep->mregs + MREGS_IACONFIG);
|
|
while ((sbus_readb(qep->mregs + MREGS_IACONFIG) & MREGS_IACONFIG_ACHNGE) != 0)
|
|
barrier();
|
|
for (i = 0; i < 8; i++) {
|
|
u8 tmp = *hbytes++;
|
|
sbus_writeb(tmp, qep->mregs + MREGS_FILTER);
|
|
}
|
|
sbus_writeb(0, qep->mregs + MREGS_IACONFIG);
|
|
}
|
|
|
|
/* Any change of the logical address filter, the physical address,
|
|
* or enabling/disabling promiscuous mode causes the MACE to disable
|
|
* the receiver. So we must re-enable them here or else the MACE
|
|
* refuses to listen to anything on the network. Sheesh, took
|
|
* me a day or two to find this bug.
|
|
*/
|
|
qep->mconfig = new_mconfig;
|
|
sbus_writeb(qep->mconfig, qep->mregs + MREGS_MCONFIG);
|
|
|
|
/* Let us get going again. */
|
|
netif_wake_queue(dev);
|
|
}
|
|
|
|
/* Ethtool support... */
|
|
static void qe_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
|
|
{
|
|
struct sunqe *qep = dev->priv;
|
|
|
|
strcpy(info->driver, "sunqe");
|
|
strcpy(info->version, "3.0");
|
|
sprintf(info->bus_info, "SBUS:%d",
|
|
qep->qe_sdev->slot);
|
|
}
|
|
|
|
static u32 qe_get_link(struct net_device *dev)
|
|
{
|
|
struct sunqe *qep = dev->priv;
|
|
void __iomem *mregs = qep->mregs;
|
|
u8 phyconfig;
|
|
|
|
spin_lock_irq(&qep->lock);
|
|
phyconfig = sbus_readb(mregs + MREGS_PHYCONFIG);
|
|
spin_unlock_irq(&qep->lock);
|
|
|
|
return (phyconfig & MREGS_PHYCONFIG_LSTAT);
|
|
}
|
|
|
|
static struct ethtool_ops qe_ethtool_ops = {
|
|
.get_drvinfo = qe_get_drvinfo,
|
|
.get_link = qe_get_link,
|
|
};
|
|
|
|
/* This is only called once at boot time for each card probed. */
|
|
static inline void qec_init_once(struct sunqec *qecp, struct sbus_dev *qsdev)
|
|
{
|
|
u8 bsizes = qecp->qec_bursts;
|
|
|
|
if (sbus_can_burst64(qsdev) && (bsizes & DMA_BURST64)) {
|
|
sbus_writel(GLOB_CTRL_B64, qecp->gregs + GLOB_CTRL);
|
|
} else if (bsizes & DMA_BURST32) {
|
|
sbus_writel(GLOB_CTRL_B32, qecp->gregs + GLOB_CTRL);
|
|
} else {
|
|
sbus_writel(GLOB_CTRL_B16, qecp->gregs + GLOB_CTRL);
|
|
}
|
|
|
|
/* Packetsize only used in 100baseT BigMAC configurations,
|
|
* set it to zero just to be on the safe side.
|
|
*/
|
|
sbus_writel(GLOB_PSIZE_2048, qecp->gregs + GLOB_PSIZE);
|
|
|
|
/* Set the local memsize register, divided up to one piece per QE channel. */
|
|
sbus_writel((qsdev->reg_addrs[1].reg_size >> 2),
|
|
qecp->gregs + GLOB_MSIZE);
|
|
|
|
/* Divide up the local QEC memory amongst the 4 QE receiver and
|
|
* transmitter FIFOs. Basically it is (total / 2 / num_channels).
|
|
*/
|
|
sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1,
|
|
qecp->gregs + GLOB_TSIZE);
|
|
sbus_writel((qsdev->reg_addrs[1].reg_size >> 2) >> 1,
|
|
qecp->gregs + GLOB_RSIZE);
|
|
}
|
|
|
|
/* Four QE's per QEC card. */
|
|
static int __init qec_ether_init(struct net_device *dev, struct sbus_dev *sdev)
|
|
{
|
|
static unsigned version_printed;
|
|
struct net_device *qe_devs[4];
|
|
struct sunqe *qeps[4];
|
|
struct sbus_dev *qesdevs[4];
|
|
struct sbus_dev *child;
|
|
struct sunqec *qecp = NULL;
|
|
u8 bsizes, bsizes_more;
|
|
int i, j, res = -ENOMEM;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
qe_devs[i] = alloc_etherdev(sizeof(struct sunqe));
|
|
if (!qe_devs[i])
|
|
goto out;
|
|
}
|
|
|
|
if (version_printed++ == 0)
|
|
printk(KERN_INFO "%s", version);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
qeps[i] = (struct sunqe *) qe_devs[i]->priv;
|
|
for (j = 0; j < 6; j++)
|
|
qe_devs[i]->dev_addr[j] = idprom->id_ethaddr[j];
|
|
qeps[i]->channel = i;
|
|
spin_lock_init(&qeps[i]->lock);
|
|
}
|
|
|
|
qecp = kmalloc(sizeof(struct sunqec), GFP_KERNEL);
|
|
if (qecp == NULL)
|
|
goto out1;
|
|
qecp->qec_sdev = sdev;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
qecp->qes[i] = qeps[i];
|
|
qeps[i]->dev = qe_devs[i];
|
|
qeps[i]->parent = qecp;
|
|
}
|
|
|
|
res = -ENODEV;
|
|
|
|
for (i = 0, child = sdev->child; i < 4; i++, child = child->next) {
|
|
/* Link in channel */
|
|
j = prom_getintdefault(child->prom_node, "channel#", -1);
|
|
if (j == -1)
|
|
goto out2;
|
|
qesdevs[j] = child;
|
|
}
|
|
|
|
for (i = 0; i < 4; i++)
|
|
qeps[i]->qe_sdev = qesdevs[i];
|
|
|
|
/* Now map in the registers, QEC globals first. */
|
|
qecp->gregs = sbus_ioremap(&sdev->resource[0], 0,
|
|
GLOB_REG_SIZE, "QEC Global Registers");
|
|
if (!qecp->gregs) {
|
|
printk(KERN_ERR "QuadEther: Cannot map QEC global registers.\n");
|
|
goto out2;
|
|
}
|
|
|
|
/* Make sure the QEC is in MACE mode. */
|
|
if ((sbus_readl(qecp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_MMODE) {
|
|
printk(KERN_ERR "QuadEther: AIEEE, QEC is not in MACE mode!\n");
|
|
goto out3;
|
|
}
|
|
|
|
/* Reset the QEC. */
|
|
if (qec_global_reset(qecp->gregs))
|
|
goto out3;
|
|
|
|
/* Find and set the burst sizes for the QEC, since it does
|
|
* the actual dma for all 4 channels.
|
|
*/
|
|
bsizes = prom_getintdefault(sdev->prom_node, "burst-sizes", 0xff);
|
|
bsizes &= 0xff;
|
|
bsizes_more = prom_getintdefault(sdev->bus->prom_node, "burst-sizes", 0xff);
|
|
|
|
if (bsizes_more != 0xff)
|
|
bsizes &= bsizes_more;
|
|
if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
|
|
(bsizes & DMA_BURST32)==0)
|
|
bsizes = (DMA_BURST32 - 1);
|
|
|
|
qecp->qec_bursts = bsizes;
|
|
|
|
/* Perform one time QEC initialization, we never touch the QEC
|
|
* globals again after this.
|
|
*/
|
|
qec_init_once(qecp, sdev);
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
struct sunqe *qe = qeps[i];
|
|
/* Map in QEC per-channel control registers. */
|
|
qe->qcregs = sbus_ioremap(&qe->qe_sdev->resource[0], 0,
|
|
CREG_REG_SIZE, "QEC Channel Registers");
|
|
if (!qe->qcregs) {
|
|
printk(KERN_ERR "QuadEther: Cannot map QE %d's channel registers.\n", i);
|
|
goto out4;
|
|
}
|
|
|
|
/* Map in per-channel AMD MACE registers. */
|
|
qe->mregs = sbus_ioremap(&qe->qe_sdev->resource[1], 0,
|
|
MREGS_REG_SIZE, "QE MACE Registers");
|
|
if (!qe->mregs) {
|
|
printk(KERN_ERR "QuadEther: Cannot map QE %d's MACE registers.\n", i);
|
|
goto out4;
|
|
}
|
|
|
|
qe->qe_block = sbus_alloc_consistent(qe->qe_sdev,
|
|
PAGE_SIZE,
|
|
&qe->qblock_dvma);
|
|
qe->buffers = sbus_alloc_consistent(qe->qe_sdev,
|
|
sizeof(struct sunqe_buffers),
|
|
&qe->buffers_dvma);
|
|
if (qe->qe_block == NULL || qe->qblock_dvma == 0 ||
|
|
qe->buffers == NULL || qe->buffers_dvma == 0) {
|
|
goto out4;
|
|
}
|
|
|
|
/* Stop this QE. */
|
|
qe_stop(qe);
|
|
}
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
SET_MODULE_OWNER(qe_devs[i]);
|
|
qe_devs[i]->open = qe_open;
|
|
qe_devs[i]->stop = qe_close;
|
|
qe_devs[i]->hard_start_xmit = qe_start_xmit;
|
|
qe_devs[i]->get_stats = qe_get_stats;
|
|
qe_devs[i]->set_multicast_list = qe_set_multicast;
|
|
qe_devs[i]->tx_timeout = qe_tx_timeout;
|
|
qe_devs[i]->watchdog_timeo = 5*HZ;
|
|
qe_devs[i]->irq = sdev->irqs[0];
|
|
qe_devs[i]->dma = 0;
|
|
qe_devs[i]->ethtool_ops = &qe_ethtool_ops;
|
|
}
|
|
|
|
/* QEC receives interrupts from each QE, then it sends the actual
|
|
* IRQ to the cpu itself. Since QEC is the single point of
|
|
* interrupt for all QE channels we register the IRQ handler
|
|
* for it now.
|
|
*/
|
|
if (request_irq(sdev->irqs[0], &qec_interrupt,
|
|
SA_SHIRQ, "QuadEther", (void *) qecp)) {
|
|
printk(KERN_ERR "QuadEther: Can't register QEC master irq handler.\n");
|
|
res = -EAGAIN;
|
|
goto out4;
|
|
}
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
if (register_netdev(qe_devs[i]) != 0)
|
|
goto out5;
|
|
}
|
|
|
|
/* Report the QE channels. */
|
|
for (i = 0; i < 4; i++) {
|
|
printk(KERN_INFO "%s: QuadEthernet channel[%d] ", qe_devs[i]->name, i);
|
|
for (j = 0; j < 6; j++)
|
|
printk ("%2.2x%c",
|
|
qe_devs[i]->dev_addr[j],
|
|
j == 5 ? ' ': ':');
|
|
printk("\n");
|
|
}
|
|
|
|
/* We are home free at this point, link the qe's into
|
|
* the master list for later driver exit.
|
|
*/
|
|
qecp->next_module = root_qec_dev;
|
|
root_qec_dev = qecp;
|
|
|
|
return 0;
|
|
|
|
out5:
|
|
while (i--)
|
|
unregister_netdev(qe_devs[i]);
|
|
free_irq(sdev->irqs[0], (void *)qecp);
|
|
out4:
|
|
for (i = 0; i < 4; i++) {
|
|
struct sunqe *qe = (struct sunqe *)qe_devs[i]->priv;
|
|
|
|
if (qe->qcregs)
|
|
sbus_iounmap(qe->qcregs, CREG_REG_SIZE);
|
|
if (qe->mregs)
|
|
sbus_iounmap(qe->mregs, MREGS_REG_SIZE);
|
|
if (qe->qe_block)
|
|
sbus_free_consistent(qe->qe_sdev,
|
|
PAGE_SIZE,
|
|
qe->qe_block,
|
|
qe->qblock_dvma);
|
|
if (qe->buffers)
|
|
sbus_free_consistent(qe->qe_sdev,
|
|
sizeof(struct sunqe_buffers),
|
|
qe->buffers,
|
|
qe->buffers_dvma);
|
|
}
|
|
out3:
|
|
sbus_iounmap(qecp->gregs, GLOB_REG_SIZE);
|
|
out2:
|
|
kfree(qecp);
|
|
out1:
|
|
i = 4;
|
|
out:
|
|
while (i--)
|
|
free_netdev(qe_devs[i]);
|
|
return res;
|
|
}
|
|
|
|
static int __init qec_match(struct sbus_dev *sdev)
|
|
{
|
|
struct sbus_dev *sibling;
|
|
int i;
|
|
|
|
if (strcmp(sdev->prom_name, "qec") != 0)
|
|
return 0;
|
|
|
|
/* QEC can be parent of either QuadEthernet or BigMAC
|
|
* children. Do not confuse this with qfe/SUNW,qfe
|
|
* which is a quad-happymeal card and handled by
|
|
* a different driver.
|
|
*/
|
|
sibling = sdev->child;
|
|
for (i = 0; i < 4; i++) {
|
|
if (sibling == NULL)
|
|
return 0;
|
|
if (strcmp(sibling->prom_name, "qe") != 0)
|
|
return 0;
|
|
sibling = sibling->next;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int __init qec_probe(void)
|
|
{
|
|
struct net_device *dev = NULL;
|
|
struct sbus_bus *bus;
|
|
struct sbus_dev *sdev = NULL;
|
|
static int called;
|
|
int cards = 0, v;
|
|
|
|
root_qec_dev = NULL;
|
|
|
|
if (called)
|
|
return -ENODEV;
|
|
called++;
|
|
|
|
for_each_sbus(bus) {
|
|
for_each_sbusdev(sdev, bus) {
|
|
if (cards)
|
|
dev = NULL;
|
|
|
|
if (qec_match(sdev)) {
|
|
cards++;
|
|
if ((v = qec_ether_init(dev, sdev)))
|
|
return v;
|
|
}
|
|
}
|
|
}
|
|
if (!cards)
|
|
return -ENODEV;
|
|
return 0;
|
|
}
|
|
|
|
static void __exit qec_cleanup(void)
|
|
{
|
|
struct sunqec *next_qec;
|
|
int i;
|
|
|
|
while (root_qec_dev) {
|
|
next_qec = root_qec_dev->next_module;
|
|
|
|
/* Release all four QE channels, then the QEC itself. */
|
|
for (i = 0; i < 4; i++) {
|
|
unregister_netdev(root_qec_dev->qes[i]->dev);
|
|
sbus_iounmap(root_qec_dev->qes[i]->qcregs, CREG_REG_SIZE);
|
|
sbus_iounmap(root_qec_dev->qes[i]->mregs, MREGS_REG_SIZE);
|
|
sbus_free_consistent(root_qec_dev->qes[i]->qe_sdev,
|
|
PAGE_SIZE,
|
|
root_qec_dev->qes[i]->qe_block,
|
|
root_qec_dev->qes[i]->qblock_dvma);
|
|
sbus_free_consistent(root_qec_dev->qes[i]->qe_sdev,
|
|
sizeof(struct sunqe_buffers),
|
|
root_qec_dev->qes[i]->buffers,
|
|
root_qec_dev->qes[i]->buffers_dvma);
|
|
free_netdev(root_qec_dev->qes[i]->dev);
|
|
}
|
|
free_irq(root_qec_dev->qec_sdev->irqs[0], (void *)root_qec_dev);
|
|
sbus_iounmap(root_qec_dev->gregs, GLOB_REG_SIZE);
|
|
kfree(root_qec_dev);
|
|
root_qec_dev = next_qec;
|
|
}
|
|
}
|
|
|
|
module_init(qec_probe);
|
|
module_exit(qec_cleanup);
|