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![David S. Miller](/assets/img/avatar_default.png)
Based upon a patch from Hareesh Nagarajan. Signed-off-by: David S. Miller <davem@davemloft.net>
649 lines
16 KiB
C
649 lines
16 KiB
C
/* cg14.c: CGFOURTEEN frame buffer driver
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*
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* Copyright (C) 2003 David S. Miller (davem@redhat.com)
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* Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
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* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
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*
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* Driver layout based loosely on tgafb.c, see that file for credits.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/fb.h>
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#include <linux/mm.h>
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#include <asm/io.h>
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#include <asm/sbus.h>
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#include <asm/oplib.h>
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#include <asm/fbio.h>
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#include "sbuslib.h"
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/*
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* Local functions.
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*/
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static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
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unsigned, struct fb_info *);
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static int cg14_mmap(struct fb_info *, struct file *, struct vm_area_struct *);
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static int cg14_ioctl(struct inode *, struct file *, unsigned int,
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unsigned long, struct fb_info *);
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static int cg14_pan_display(struct fb_var_screeninfo *, struct fb_info *);
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/*
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* Frame buffer operations
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*/
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static struct fb_ops cg14_ops = {
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.owner = THIS_MODULE,
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.fb_setcolreg = cg14_setcolreg,
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.fb_pan_display = cg14_pan_display,
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.fb_fillrect = cfb_fillrect,
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.fb_copyarea = cfb_copyarea,
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.fb_imageblit = cfb_imageblit,
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.fb_mmap = cg14_mmap,
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.fb_ioctl = cg14_ioctl,
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#ifdef CONFIG_COMPAT
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.fb_compat_ioctl = sbusfb_compat_ioctl,
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#endif
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};
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#define CG14_MCR_INTENABLE_SHIFT 7
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#define CG14_MCR_INTENABLE_MASK 0x80
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#define CG14_MCR_VIDENABLE_SHIFT 6
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#define CG14_MCR_VIDENABLE_MASK 0x40
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#define CG14_MCR_PIXMODE_SHIFT 4
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#define CG14_MCR_PIXMODE_MASK 0x30
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#define CG14_MCR_TMR_SHIFT 2
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#define CG14_MCR_TMR_MASK 0x0c
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#define CG14_MCR_TMENABLE_SHIFT 1
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#define CG14_MCR_TMENABLE_MASK 0x02
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#define CG14_MCR_RESET_SHIFT 0
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#define CG14_MCR_RESET_MASK 0x01
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#define CG14_REV_REVISION_SHIFT 4
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#define CG14_REV_REVISION_MASK 0xf0
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#define CG14_REV_IMPL_SHIFT 0
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#define CG14_REV_IMPL_MASK 0x0f
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#define CG14_VBR_FRAMEBASE_SHIFT 12
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#define CG14_VBR_FRAMEBASE_MASK 0x00fff000
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#define CG14_VMCR1_SETUP_SHIFT 0
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#define CG14_VMCR1_SETUP_MASK 0x000001ff
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#define CG14_VMCR1_VCONFIG_SHIFT 9
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#define CG14_VMCR1_VCONFIG_MASK 0x00000e00
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#define CG14_VMCR2_REFRESH_SHIFT 0
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#define CG14_VMCR2_REFRESH_MASK 0x00000001
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#define CG14_VMCR2_TESTROWCNT_SHIFT 1
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#define CG14_VMCR2_TESTROWCNT_MASK 0x00000002
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#define CG14_VMCR2_FBCONFIG_SHIFT 2
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#define CG14_VMCR2_FBCONFIG_MASK 0x0000000c
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#define CG14_VCR_REFRESHREQ_SHIFT 0
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#define CG14_VCR_REFRESHREQ_MASK 0x000003ff
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#define CG14_VCR1_REFRESHENA_SHIFT 10
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#define CG14_VCR1_REFRESHENA_MASK 0x00000400
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#define CG14_VCA_CAD_SHIFT 0
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#define CG14_VCA_CAD_MASK 0x000003ff
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#define CG14_VCA_VERS_SHIFT 10
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#define CG14_VCA_VERS_MASK 0x00000c00
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#define CG14_VCA_RAMSPEED_SHIFT 12
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#define CG14_VCA_RAMSPEED_MASK 0x00001000
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#define CG14_VCA_8MB_SHIFT 13
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#define CG14_VCA_8MB_MASK 0x00002000
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#define CG14_MCR_PIXMODE_8 0
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#define CG14_MCR_PIXMODE_16 2
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#define CG14_MCR_PIXMODE_32 3
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struct cg14_regs{
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volatile u8 mcr; /* Master Control Reg */
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volatile u8 ppr; /* Packed Pixel Reg */
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volatile u8 tms[2]; /* Test Mode Status Regs */
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volatile u8 msr; /* Master Status Reg */
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volatile u8 fsr; /* Fault Status Reg */
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volatile u8 rev; /* Revision & Impl */
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volatile u8 ccr; /* Clock Control Reg */
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volatile u32 tmr; /* Test Mode Read Back */
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volatile u8 mod; /* Monitor Operation Data Reg */
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volatile u8 acr; /* Aux Control */
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u8 xxx0[6];
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volatile u16 hct; /* Hor Counter */
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volatile u16 vct; /* Vert Counter */
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volatile u16 hbs; /* Hor Blank Start */
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volatile u16 hbc; /* Hor Blank Clear */
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volatile u16 hss; /* Hor Sync Start */
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volatile u16 hsc; /* Hor Sync Clear */
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volatile u16 csc; /* Composite Sync Clear */
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volatile u16 vbs; /* Vert Blank Start */
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volatile u16 vbc; /* Vert Blank Clear */
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volatile u16 vss; /* Vert Sync Start */
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volatile u16 vsc; /* Vert Sync Clear */
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volatile u16 xcs;
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volatile u16 xcc;
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volatile u16 fsa; /* Fault Status Address */
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volatile u16 adr; /* Address Registers */
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u8 xxx1[0xce];
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volatile u8 pcg[0x100]; /* Pixel Clock Generator */
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volatile u32 vbr; /* Frame Base Row */
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volatile u32 vmcr; /* VBC Master Control */
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volatile u32 vcr; /* VBC refresh */
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volatile u32 vca; /* VBC Config */
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};
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#define CG14_CCR_ENABLE 0x04
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#define CG14_CCR_SELECT 0x02 /* HW/Full screen */
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struct cg14_cursor {
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volatile u32 cpl0[32]; /* Enable plane 0 */
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volatile u32 cpl1[32]; /* Color selection plane */
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volatile u8 ccr; /* Cursor Control Reg */
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u8 xxx0[3];
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volatile u16 cursx; /* Cursor x,y position */
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volatile u16 cursy; /* Cursor x,y position */
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volatile u32 color0;
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volatile u32 color1;
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u32 xxx1[0x1bc];
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volatile u32 cpl0i[32]; /* Enable plane 0 autoinc */
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volatile u32 cpl1i[32]; /* Color selection autoinc */
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};
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struct cg14_dac {
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volatile u8 addr; /* Address Register */
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u8 xxx0[255];
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volatile u8 glut; /* Gamma table */
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u8 xxx1[255];
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volatile u8 select; /* Register Select */
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u8 xxx2[255];
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volatile u8 mode; /* Mode Register */
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};
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struct cg14_xlut{
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volatile u8 x_xlut [256];
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volatile u8 x_xlutd [256];
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u8 xxx0[0x600];
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volatile u8 x_xlut_inc [256];
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volatile u8 x_xlutd_inc [256];
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};
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/* Color look up table (clut) */
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/* Each one of these arrays hold the color lookup table (for 256
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* colors) for each MDI page (I assume then there should be 4 MDI
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* pages, I still wonder what they are. I have seen NeXTStep split
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* the screen in four parts, while operating in 24 bits mode. Each
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* integer holds 4 values: alpha value (transparency channel, thanks
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* go to John Stone (johns@umr.edu) from OpenBSD), red, green and blue
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*
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* I currently use the clut instead of the Xlut
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*/
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struct cg14_clut {
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u32 c_clut [256];
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u32 c_clutd [256]; /* i wonder what the 'd' is for */
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u32 c_clut_inc [256];
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u32 c_clutd_inc [256];
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};
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#define CG14_MMAP_ENTRIES 16
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struct cg14_par {
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spinlock_t lock;
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struct cg14_regs __iomem *regs;
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struct cg14_clut __iomem *clut;
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struct cg14_cursor __iomem *cursor;
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u32 flags;
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#define CG14_FLAG_BLANKED 0x00000001
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unsigned long physbase;
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unsigned long iospace;
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unsigned long fbsize;
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struct sbus_mmap_map mmap_map[CG14_MMAP_ENTRIES];
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int mode;
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int ramsize;
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struct sbus_dev *sdev;
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};
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static void __cg14_reset(struct cg14_par *par)
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{
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struct cg14_regs __iomem *regs = par->regs;
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u8 val;
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val = sbus_readb(®s->mcr);
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val &= ~(CG14_MCR_PIXMODE_MASK);
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sbus_writeb(val, ®s->mcr);
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}
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static int cg14_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
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{
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struct cg14_par *par = (struct cg14_par *) info->par;
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unsigned long flags;
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/* We just use this to catch switches out of
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* graphics mode.
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*/
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spin_lock_irqsave(&par->lock, flags);
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__cg14_reset(par);
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spin_unlock_irqrestore(&par->lock, flags);
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if (var->xoffset || var->yoffset || var->vmode)
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return -EINVAL;
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return 0;
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}
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/**
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* cg14_setcolreg - Optional function. Sets a color register.
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* @regno: boolean, 0 copy local, 1 get_user() function
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* @red: frame buffer colormap structure
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* @green: The green value which can be up to 16 bits wide
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* @blue: The blue value which can be up to 16 bits wide.
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* @transp: If supported the alpha value which can be up to 16 bits wide.
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* @info: frame buffer info structure
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*/
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static int cg14_setcolreg(unsigned regno,
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unsigned red, unsigned green, unsigned blue,
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unsigned transp, struct fb_info *info)
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{
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struct cg14_par *par = (struct cg14_par *) info->par;
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struct cg14_clut __iomem *clut = par->clut;
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unsigned long flags;
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u32 val;
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if (regno >= 256)
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return 1;
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red >>= 8;
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green >>= 8;
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blue >>= 8;
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val = (red | (green << 8) | (blue << 16));
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spin_lock_irqsave(&par->lock, flags);
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sbus_writel(val, &clut->c_clut[regno]);
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spin_unlock_irqrestore(&par->lock, flags);
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return 0;
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}
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static int cg14_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
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{
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struct cg14_par *par = (struct cg14_par *) info->par;
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return sbusfb_mmap_helper(par->mmap_map,
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par->physbase, par->fbsize,
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par->iospace, vma);
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}
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static int cg14_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
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unsigned long arg, struct fb_info *info)
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{
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struct cg14_par *par = (struct cg14_par *) info->par;
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struct cg14_regs __iomem *regs = par->regs;
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struct mdi_cfginfo kmdi, __user *mdii;
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unsigned long flags;
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int cur_mode, mode, ret = 0;
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switch (cmd) {
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case MDI_RESET:
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spin_lock_irqsave(&par->lock, flags);
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__cg14_reset(par);
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spin_unlock_irqrestore(&par->lock, flags);
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break;
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case MDI_GET_CFGINFO:
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memset(&kmdi, 0, sizeof(kmdi));
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spin_lock_irqsave(&par->lock, flags);
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kmdi.mdi_type = FBTYPE_MDICOLOR;
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kmdi.mdi_height = info->var.yres;
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kmdi.mdi_width = info->var.xres;
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kmdi.mdi_mode = par->mode;
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kmdi.mdi_pixfreq = 72; /* FIXME */
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kmdi.mdi_size = par->ramsize;
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spin_unlock_irqrestore(&par->lock, flags);
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mdii = (struct mdi_cfginfo __user *) arg;
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if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
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ret = -EFAULT;
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break;
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case MDI_SET_PIXELMODE:
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if (get_user(mode, (int __user *) arg)) {
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ret = -EFAULT;
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break;
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}
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spin_lock_irqsave(&par->lock, flags);
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cur_mode = sbus_readb(®s->mcr);
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cur_mode &= ~CG14_MCR_PIXMODE_MASK;
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switch(mode) {
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case MDI_32_PIX:
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cur_mode |= (CG14_MCR_PIXMODE_32 <<
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CG14_MCR_PIXMODE_SHIFT);
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break;
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case MDI_16_PIX:
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cur_mode |= (CG14_MCR_PIXMODE_16 <<
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CG14_MCR_PIXMODE_SHIFT);
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break;
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case MDI_8_PIX:
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break;
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default:
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ret = -ENOSYS;
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break;
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};
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if (!ret) {
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sbus_writeb(cur_mode, ®s->mcr);
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par->mode = mode;
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}
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spin_unlock_irqrestore(&par->lock, flags);
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break;
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default:
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ret = sbusfb_ioctl_helper(cmd, arg, info,
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FBTYPE_MDICOLOR, 8, par->fbsize);
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break;
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};
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return ret;
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}
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/*
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* Initialisation
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*/
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static void cg14_init_fix(struct fb_info *info, int linebytes)
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{
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struct cg14_par *par = (struct cg14_par *)info->par;
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const char *name;
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name = "cgfourteen";
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if (par->sdev)
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name = par->sdev->prom_name;
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strlcpy(info->fix.id, name, sizeof(info->fix.id));
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info->fix.type = FB_TYPE_PACKED_PIXELS;
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
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info->fix.line_length = linebytes;
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info->fix.accel = FB_ACCEL_SUN_CG14;
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}
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static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] __initdata = {
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{
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.voff = CG14_REGS,
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.poff = 0x80000000,
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.size = 0x1000
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},
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{
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.voff = CG14_XLUT,
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.poff = 0x80003000,
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.size = 0x1000
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},
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{
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.voff = CG14_CLUT1,
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.poff = 0x80004000,
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.size = 0x1000
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},
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{
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.voff = CG14_CLUT2,
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.poff = 0x80005000,
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.size = 0x1000
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},
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{
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.voff = CG14_CLUT3,
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.poff = 0x80006000,
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.size = 0x1000
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},
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{
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.voff = CG3_MMAP_OFFSET - 0x7000,
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.poff = 0x80000000,
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.size = 0x7000
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},
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{
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.voff = CG3_MMAP_OFFSET,
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.poff = 0x00000000,
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.size = SBUS_MMAP_FBSIZE(1)
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},
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{
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.voff = MDI_CURSOR_MAP,
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.poff = 0x80001000,
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.size = 0x1000
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},
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{
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.voff = MDI_CHUNKY_BGR_MAP,
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.poff = 0x01000000,
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.size = 0x400000
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},
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{
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.voff = MDI_PLANAR_X16_MAP,
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.poff = 0x02000000,
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.size = 0x200000
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},
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{
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.voff = MDI_PLANAR_C16_MAP,
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.poff = 0x02800000,
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.size = 0x200000
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},
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{
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.voff = MDI_PLANAR_X32_MAP,
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.poff = 0x03000000,
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.size = 0x100000
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},
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{
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.voff = MDI_PLANAR_B32_MAP,
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.poff = 0x03400000,
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.size = 0x100000
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},
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{
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.voff = MDI_PLANAR_G32_MAP,
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.poff = 0x03800000,
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.size = 0x100000
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},
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{
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.voff = MDI_PLANAR_R32_MAP,
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.poff = 0x03c00000,
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.size = 0x100000
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},
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{ .size = 0 }
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};
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struct all_info {
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struct fb_info info;
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struct cg14_par par;
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struct list_head list;
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};
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static LIST_HEAD(cg14_list);
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static void cg14_init_one(struct sbus_dev *sdev, int node, int parent_node)
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{
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struct all_info *all;
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unsigned long phys, rphys;
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u32 bases[6];
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int is_8mb, linebytes, i;
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if (!sdev) {
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if (prom_getproperty(node, "address",
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(char *) &bases[0], sizeof(bases)) <= 0
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|| !bases[0]) {
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printk(KERN_ERR "cg14: Device is not mapped.\n");
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return;
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}
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if (__get_iospace(bases[0]) != __get_iospace(bases[1])) {
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printk(KERN_ERR "cg14: I/O spaces don't match.\n");
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return;
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}
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}
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all = kmalloc(sizeof(*all), GFP_KERNEL);
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if (!all) {
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printk(KERN_ERR "cg14: Cannot allocate memory.\n");
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return;
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}
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memset(all, 0, sizeof(*all));
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INIT_LIST_HEAD(&all->list);
|
|
|
|
spin_lock_init(&all->par.lock);
|
|
|
|
sbusfb_fill_var(&all->info.var, node, 8);
|
|
all->info.var.red.length = 8;
|
|
all->info.var.green.length = 8;
|
|
all->info.var.blue.length = 8;
|
|
|
|
linebytes = prom_getintdefault(node, "linebytes",
|
|
all->info.var.xres);
|
|
all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
|
|
|
|
all->par.sdev = sdev;
|
|
if (sdev) {
|
|
rphys = sdev->reg_addrs[0].phys_addr;
|
|
all->par.physbase = phys = sdev->reg_addrs[1].phys_addr;
|
|
all->par.iospace = sdev->reg_addrs[0].which_io;
|
|
|
|
all->par.regs = sbus_ioremap(&sdev->resource[0], 0,
|
|
sizeof(struct cg14_regs),
|
|
"cg14 regs");
|
|
all->par.clut = sbus_ioremap(&sdev->resource[0], CG14_CLUT1,
|
|
sizeof(struct cg14_clut),
|
|
"cg14 clut");
|
|
all->par.cursor = sbus_ioremap(&sdev->resource[0], CG14_CURSORREGS,
|
|
sizeof(struct cg14_cursor),
|
|
"cg14 cursor");
|
|
all->info.screen_base = sbus_ioremap(&sdev->resource[1], 0,
|
|
all->par.fbsize, "cg14 ram");
|
|
} else {
|
|
rphys = __get_phys(bases[0]);
|
|
all->par.physbase = phys = __get_phys(bases[1]);
|
|
all->par.iospace = __get_iospace(bases[0]);
|
|
all->par.regs = (struct cg14_regs __iomem *)(unsigned long)bases[0];
|
|
all->par.clut = (struct cg14_clut __iomem *)((unsigned long)bases[0] +
|
|
CG14_CLUT1);
|
|
all->par.cursor =
|
|
(struct cg14_cursor __iomem *)((unsigned long)bases[0] +
|
|
CG14_CURSORREGS);
|
|
|
|
all->info.screen_base = (char __iomem *)(unsigned long)bases[1];
|
|
}
|
|
|
|
prom_getproperty(node, "reg", (char *) &bases[0], sizeof(bases));
|
|
is_8mb = (bases[5] == 0x800000);
|
|
|
|
if (sizeof(all->par.mmap_map) != sizeof(__cg14_mmap_map)) {
|
|
extern void __cg14_mmap_sized_wrongly(void);
|
|
|
|
__cg14_mmap_sized_wrongly();
|
|
}
|
|
|
|
memcpy(&all->par.mmap_map, &__cg14_mmap_map, sizeof(all->par.mmap_map));
|
|
for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
|
|
struct sbus_mmap_map *map = &all->par.mmap_map[i];
|
|
|
|
if (!map->size)
|
|
break;
|
|
if (map->poff & 0x80000000)
|
|
map->poff = (map->poff & 0x7fffffff) + rphys - phys;
|
|
if (is_8mb &&
|
|
map->size >= 0x100000 &&
|
|
map->size <= 0x400000)
|
|
map->size *= 2;
|
|
}
|
|
|
|
all->par.mode = MDI_8_PIX;
|
|
all->par.ramsize = (is_8mb ? 0x800000 : 0x400000);
|
|
|
|
all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
|
|
all->info.fbops = &cg14_ops;
|
|
all->info.par = &all->par;
|
|
|
|
__cg14_reset(&all->par);
|
|
|
|
if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
|
|
printk(KERN_ERR "cg14: Could not allocate color map.\n");
|
|
kfree(all);
|
|
return;
|
|
}
|
|
fb_set_cmap(&all->info.cmap, &all->info);
|
|
|
|
cg14_init_fix(&all->info, linebytes);
|
|
|
|
if (register_framebuffer(&all->info) < 0) {
|
|
printk(KERN_ERR "cg14: Could not register framebuffer.\n");
|
|
fb_dealloc_cmap(&all->info.cmap);
|
|
kfree(all);
|
|
return;
|
|
}
|
|
|
|
list_add(&all->list, &cg14_list);
|
|
|
|
printk("cg14: cgfourteen at %lx:%lx, %dMB\n",
|
|
all->par.iospace, all->par.physbase, all->par.ramsize >> 20);
|
|
|
|
}
|
|
|
|
int __init cg14_init(void)
|
|
{
|
|
struct sbus_bus *sbus;
|
|
struct sbus_dev *sdev;
|
|
|
|
if (fb_get_options("cg14fb", NULL))
|
|
return -ENODEV;
|
|
|
|
#ifdef CONFIG_SPARC32
|
|
{
|
|
int root, node;
|
|
|
|
root = prom_getchild(prom_root_node);
|
|
root = prom_searchsiblings(root, "obio");
|
|
if (root) {
|
|
node = prom_searchsiblings(prom_getchild(root),
|
|
"cgfourteen");
|
|
if (node)
|
|
cg14_init_one(NULL, node, root);
|
|
}
|
|
}
|
|
#endif
|
|
for_all_sbusdev(sdev, sbus) {
|
|
if (!strcmp(sdev->prom_name, "cgfourteen"))
|
|
cg14_init_one(sdev, sdev->prom_node, sbus->prom_node);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __exit cg14_exit(void)
|
|
{
|
|
struct list_head *pos, *tmp;
|
|
|
|
list_for_each_safe(pos, tmp, &cg14_list) {
|
|
struct all_info *all = list_entry(pos, typeof(*all), list);
|
|
|
|
unregister_framebuffer(&all->info);
|
|
fb_dealloc_cmap(&all->info.cmap);
|
|
kfree(all);
|
|
}
|
|
}
|
|
|
|
int __init
|
|
cg14_setup(char *arg)
|
|
{
|
|
/* No cmdline options yet... */
|
|
return 0;
|
|
}
|
|
|
|
module_init(cg14_init);
|
|
|
|
#ifdef MODULE
|
|
module_exit(cg14_exit);
|
|
#endif
|
|
|
|
MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
|
|
MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
|
|
MODULE_LICENSE("GPL");
|