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![Linus Torvalds](/assets/img/avatar_default.png)
Pull slave-dmaengine updates from Vinod Koul: "This pull brings: - Andy's DW driver updates - Guennadi's sh driver updates - Pl08x driver fixes from Tomasz & Alban - Improvements to mmp_pdma by Daniel - TI EDMA fixes by Joel - New drivers: - Hisilicon k3dma driver - Renesas rcar dma driver - New API for publishing slave driver capablities - Various fixes across the subsystem by Andy, Jingoo, Sachin etc..." * 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (94 commits) dma: edma: Remove limits on number of slots dma: edma: Leave linked to Null slot instead of DUMMY slot dma: edma: Find missed events and issue them ARM: edma: Add function to manually trigger an EDMA channel dma: edma: Write out and handle MAX_NR_SG at a given time dma: edma: Setup parameters to DMA MAX_NR_SG at a time dmaengine: pl330: use dma_set_max_seg_size to set the sg limit dmaengine: dma_slave_caps: remove sg entries dma: replace devm_request_and_ioremap by devm_ioremap_resource dma: ste_dma40: Fix potential null pointer dereference dma: ste_dma40: Remove duplicate const dma: imx-dma: Remove redundant NULL check dma: dmagengine: fix function names in comments dma: add driver for R-Car HPB-DMAC dma: k3dma: use devm_ioremap_resource() instead of devm_request_and_ioremap() dma: imx-sdma: Staticize sdma_driver_data structures pch_dma: Add MODULE_DEVICE_TABLE dmaengine: PL08x: Add cyclic transfer support dmaengine: PL08x: Fix reading the byte count in cctl dmaengine: PL08x: Add support for different maximum transfer size ...
1087 lines
35 KiB
C
1087 lines
35 KiB
C
/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef LINUX_DMAENGINE_H
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#define LINUX_DMAENGINE_H
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#include <linux/device.h>
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#include <linux/uio.h>
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#include <linux/bug.h>
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#include <linux/scatterlist.h>
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#include <linux/bitmap.h>
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#include <linux/types.h>
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#include <asm/page.h>
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/**
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* typedef dma_cookie_t - an opaque DMA cookie
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*
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* if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
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*/
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typedef s32 dma_cookie_t;
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#define DMA_MIN_COOKIE 1
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#define DMA_MAX_COOKIE INT_MAX
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static inline int dma_submit_error(dma_cookie_t cookie)
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{
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return cookie < 0 ? cookie : 0;
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}
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/**
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* enum dma_status - DMA transaction status
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* @DMA_SUCCESS: transaction completed successfully
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* @DMA_IN_PROGRESS: transaction not yet processed
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* @DMA_PAUSED: transaction is paused
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* @DMA_ERROR: transaction failed
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*/
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enum dma_status {
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DMA_SUCCESS,
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DMA_IN_PROGRESS,
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DMA_PAUSED,
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DMA_ERROR,
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};
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/**
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* enum dma_transaction_type - DMA transaction types/indexes
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*
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* Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
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* automatically set as dma devices are registered.
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*/
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enum dma_transaction_type {
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DMA_MEMCPY,
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DMA_XOR,
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DMA_PQ,
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DMA_XOR_VAL,
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DMA_PQ_VAL,
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DMA_INTERRUPT,
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DMA_SG,
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DMA_PRIVATE,
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DMA_ASYNC_TX,
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DMA_SLAVE,
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DMA_CYCLIC,
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DMA_INTERLEAVE,
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/* last transaction type for creation of the capabilities mask */
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DMA_TX_TYPE_END,
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};
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/**
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* enum dma_transfer_direction - dma transfer mode and direction indicator
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* @DMA_MEM_TO_MEM: Async/Memcpy mode
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* @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
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* @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
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* @DMA_DEV_TO_DEV: Slave mode & From Device to Device
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*/
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enum dma_transfer_direction {
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DMA_MEM_TO_MEM,
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DMA_MEM_TO_DEV,
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DMA_DEV_TO_MEM,
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DMA_DEV_TO_DEV,
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DMA_TRANS_NONE,
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};
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/**
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* Interleaved Transfer Request
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* ----------------------------
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* A chunk is collection of contiguous bytes to be transfered.
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* The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
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* ICGs may or maynot change between chunks.
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* A FRAME is the smallest series of contiguous {chunk,icg} pairs,
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* that when repeated an integral number of times, specifies the transfer.
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* A transfer template is specification of a Frame, the number of times
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* it is to be repeated and other per-transfer attributes.
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*
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* Practically, a client driver would have ready a template for each
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* type of transfer it is going to need during its lifetime and
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* set only 'src_start' and 'dst_start' before submitting the requests.
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*
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*
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* | Frame-1 | Frame-2 | ~ | Frame-'numf' |
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* |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
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*
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* == Chunk size
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* ... ICG
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*/
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/**
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* struct data_chunk - Element of scatter-gather list that makes a frame.
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* @size: Number of bytes to read from source.
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* size_dst := fn(op, size_src), so doesn't mean much for destination.
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* @icg: Number of bytes to jump after last src/dst address of this
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* chunk and before first src/dst address for next chunk.
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* Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
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* Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
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*/
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struct data_chunk {
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size_t size;
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size_t icg;
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};
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/**
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* struct dma_interleaved_template - Template to convey DMAC the transfer pattern
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* and attributes.
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* @src_start: Bus address of source for the first chunk.
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* @dst_start: Bus address of destination for the first chunk.
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* @dir: Specifies the type of Source and Destination.
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* @src_inc: If the source address increments after reading from it.
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* @dst_inc: If the destination address increments after writing to it.
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* @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
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* Otherwise, source is read contiguously (icg ignored).
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* Ignored if src_inc is false.
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* @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
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* Otherwise, destination is filled contiguously (icg ignored).
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* Ignored if dst_inc is false.
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* @numf: Number of frames in this template.
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* @frame_size: Number of chunks in a frame i.e, size of sgl[].
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* @sgl: Array of {chunk,icg} pairs that make up a frame.
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*/
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struct dma_interleaved_template {
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dma_addr_t src_start;
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dma_addr_t dst_start;
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enum dma_transfer_direction dir;
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bool src_inc;
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bool dst_inc;
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bool src_sgl;
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bool dst_sgl;
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size_t numf;
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size_t frame_size;
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struct data_chunk sgl[0];
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};
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/**
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* enum dma_ctrl_flags - DMA flags to augment operation preparation,
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* control completion, and communicate status.
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* @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
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* this transaction
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* @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
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* acknowledges receipt, i.e. has has a chance to establish any dependency
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* chains
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* @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
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* @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
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* @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
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* (if not set, do the source dma-unmapping as page)
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* @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
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* (if not set, do the destination dma-unmapping as page)
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* @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
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* @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
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* @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
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* sources that were the result of a previous operation, in the case of a PQ
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* operation it continues the calculation with new sources
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* @DMA_PREP_FENCE - tell the driver that subsequent operations depend
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* on the result of this operation
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*/
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enum dma_ctrl_flags {
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DMA_PREP_INTERRUPT = (1 << 0),
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DMA_CTRL_ACK = (1 << 1),
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DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
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DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
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DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
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DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
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DMA_PREP_PQ_DISABLE_P = (1 << 6),
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DMA_PREP_PQ_DISABLE_Q = (1 << 7),
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DMA_PREP_CONTINUE = (1 << 8),
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DMA_PREP_FENCE = (1 << 9),
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};
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/**
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* enum dma_ctrl_cmd - DMA operations that can optionally be exercised
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* on a running channel.
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* @DMA_TERMINATE_ALL: terminate all ongoing transfers
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* @DMA_PAUSE: pause ongoing transfers
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* @DMA_RESUME: resume paused transfer
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* @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
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* that need to runtime reconfigure the slave channels (as opposed to passing
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* configuration data in statically from the platform). An additional
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* argument of struct dma_slave_config must be passed in with this
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* command.
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* @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
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* into external start mode.
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*/
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enum dma_ctrl_cmd {
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DMA_TERMINATE_ALL,
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DMA_PAUSE,
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DMA_RESUME,
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DMA_SLAVE_CONFIG,
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FSLDMA_EXTERNAL_START,
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};
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/**
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* enum sum_check_bits - bit position of pq_check_flags
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*/
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enum sum_check_bits {
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SUM_CHECK_P = 0,
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SUM_CHECK_Q = 1,
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};
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/**
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* enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
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* @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
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* @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
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*/
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enum sum_check_flags {
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SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
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SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
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};
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/**
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* dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
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* See linux/cpumask.h
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*/
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typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
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/**
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* struct dma_chan_percpu - the per-CPU part of struct dma_chan
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* @memcpy_count: transaction counter
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* @bytes_transferred: byte counter
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*/
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struct dma_chan_percpu {
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/* stats */
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unsigned long memcpy_count;
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unsigned long bytes_transferred;
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};
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/**
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* struct dma_chan - devices supply DMA channels, clients use them
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* @device: ptr to the dma device who supplies this channel, always !%NULL
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* @cookie: last cookie value returned to client
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* @completed_cookie: last completed cookie for this channel
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* @chan_id: channel ID for sysfs
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* @dev: class device for sysfs
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* @device_node: used to add this to the device chan list
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* @local: per-cpu pointer to a struct dma_chan_percpu
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* @client-count: how many clients are using this channel
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* @table_count: number of appearances in the mem-to-mem allocation table
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* @private: private data for certain client-channel associations
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*/
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struct dma_chan {
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struct dma_device *device;
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dma_cookie_t cookie;
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dma_cookie_t completed_cookie;
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/* sysfs */
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int chan_id;
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struct dma_chan_dev *dev;
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struct list_head device_node;
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struct dma_chan_percpu __percpu *local;
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int client_count;
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int table_count;
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void *private;
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};
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/**
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* struct dma_chan_dev - relate sysfs device node to backing channel device
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* @chan - driver channel device
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* @device - sysfs device
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* @dev_id - parent dma_device dev_id
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* @idr_ref - reference count to gate release of dma_device dev_id
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*/
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struct dma_chan_dev {
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struct dma_chan *chan;
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struct device device;
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int dev_id;
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atomic_t *idr_ref;
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};
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/**
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* enum dma_slave_buswidth - defines bus with of the DMA slave
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* device, source or target buses
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*/
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enum dma_slave_buswidth {
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DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
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DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
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DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
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DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
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DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
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};
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/**
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* struct dma_slave_config - dma slave channel runtime config
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* @direction: whether the data shall go in or out on this slave
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* channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
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* legal values, DMA_BIDIRECTIONAL is not acceptable since we
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* need to differentiate source and target addresses.
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* @src_addr: this is the physical address where DMA slave data
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* should be read (RX), if the source is memory this argument is
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* ignored.
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* @dst_addr: this is the physical address where DMA slave data
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* should be written (TX), if the source is memory this argument
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* is ignored.
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* @src_addr_width: this is the width in bytes of the source (RX)
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* register where DMA data shall be read. If the source
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* is memory this may be ignored depending on architecture.
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* Legal values: 1, 2, 4, 8.
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* @dst_addr_width: same as src_addr_width but for destination
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* target (TX) mutatis mutandis.
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* @src_maxburst: the maximum number of words (note: words, as in
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* units of the src_addr_width member, not bytes) that can be sent
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* in one burst to the device. Typically something like half the
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* FIFO depth on I/O peripherals so you don't overflow it. This
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* may or may not be applicable on memory sources.
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* @dst_maxburst: same as src_maxburst but for destination target
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* mutatis mutandis.
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* @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
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* with 'true' if peripheral should be flow controller. Direction will be
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* selected at Runtime.
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* @slave_id: Slave requester id. Only valid for slave channels. The dma
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* slave peripheral will have unique id as dma requester which need to be
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* pass as slave config.
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*
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* This struct is passed in as configuration data to a DMA engine
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* in order to set up a certain channel for DMA transport at runtime.
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* The DMA device/engine has to provide support for an additional
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* command in the channel config interface, DMA_SLAVE_CONFIG
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* and this struct will then be passed in as an argument to the
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* DMA engine device_control() function.
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*
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* The rationale for adding configuration information to this struct
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* is as follows: if it is likely that most DMA slave controllers in
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* the world will support the configuration option, then make it
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* generic. If not: if it is fixed so that it be sent in static from
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* the platform data, then prefer to do that. Else, if it is neither
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* fixed at runtime, nor generic enough (such as bus mastership on
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* some CPU family and whatnot) then create a custom slave config
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* struct and pass that, then make this config a member of that
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* struct, if applicable.
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*/
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struct dma_slave_config {
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enum dma_transfer_direction direction;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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enum dma_slave_buswidth src_addr_width;
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enum dma_slave_buswidth dst_addr_width;
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u32 src_maxburst;
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u32 dst_maxburst;
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bool device_fc;
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unsigned int slave_id;
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};
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/* struct dma_slave_caps - expose capabilities of a slave channel only
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*
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* @src_addr_widths: bit mask of src addr widths the channel supports
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* @dstn_addr_widths: bit mask of dstn addr widths the channel supports
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* @directions: bit mask of slave direction the channel supported
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* since the enum dma_transfer_direction is not defined as bits for each
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* type of direction, the dma controller should fill (1 << <TYPE>) and same
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* should be checked by controller as well
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* @cmd_pause: true, if pause and thereby resume is supported
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* @cmd_terminate: true, if terminate cmd is supported
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*/
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struct dma_slave_caps {
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u32 src_addr_widths;
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u32 dstn_addr_widths;
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u32 directions;
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bool cmd_pause;
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bool cmd_terminate;
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};
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static inline const char *dma_chan_name(struct dma_chan *chan)
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{
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return dev_name(&chan->dev->device);
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}
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void dma_chan_cleanup(struct kref *kref);
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/**
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* typedef dma_filter_fn - callback filter for dma_request_channel
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* @chan: channel to be reviewed
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* @filter_param: opaque parameter passed through dma_request_channel
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*
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* When this optional parameter is specified in a call to dma_request_channel a
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* suitable channel is passed to this routine for further dispositioning before
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* being returned. Where 'suitable' indicates a non-busy channel that
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* satisfies the given capability mask. It returns 'true' to indicate that the
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* channel is suitable.
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*/
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typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
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typedef void (*dma_async_tx_callback)(void *dma_async_param);
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/**
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* struct dma_async_tx_descriptor - async transaction descriptor
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* ---dma generic offload fields---
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* @cookie: tracking cookie for this transaction, set to -EBUSY if
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* this tx is sitting on a dependency list
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* @flags: flags to augment operation preparation, control completion, and
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* communicate status
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* @phys: physical address of the descriptor
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* @chan: target channel for this operation
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* @tx_submit: set the prepared descriptor(s) to be executed by the engine
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* @callback: routine to call after this operation is complete
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* @callback_param: general parameter to pass to the callback routine
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* ---async_tx api specific fields---
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* @next: at completion submit this descriptor
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* @parent: pointer to the next level up in the dependency chain
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* @lock: protect the parent and next pointers
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*/
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struct dma_async_tx_descriptor {
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dma_cookie_t cookie;
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enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
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dma_addr_t phys;
|
|
struct dma_chan *chan;
|
|
dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
|
|
dma_async_tx_callback callback;
|
|
void *callback_param;
|
|
#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
|
struct dma_async_tx_descriptor *next;
|
|
struct dma_async_tx_descriptor *parent;
|
|
spinlock_t lock;
|
|
#endif
|
|
};
|
|
|
|
#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
|
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
}
|
|
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
}
|
|
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
|
|
{
|
|
BUG();
|
|
}
|
|
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
}
|
|
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
}
|
|
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
return NULL;
|
|
}
|
|
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
#else
|
|
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
spin_lock_bh(&txd->lock);
|
|
}
|
|
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
spin_unlock_bh(&txd->lock);
|
|
}
|
|
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
|
|
{
|
|
txd->next = next;
|
|
next->parent = txd;
|
|
}
|
|
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
txd->parent = NULL;
|
|
}
|
|
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
txd->next = NULL;
|
|
}
|
|
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
return txd->parent;
|
|
}
|
|
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
|
|
{
|
|
return txd->next;
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* struct dma_tx_state - filled in to report the status of
|
|
* a transfer.
|
|
* @last: last completed DMA cookie
|
|
* @used: last issued DMA cookie (i.e. the one in progress)
|
|
* @residue: the remaining number of bytes left to transmit
|
|
* on the selected transfer for states DMA_IN_PROGRESS and
|
|
* DMA_PAUSED if this is implemented in the driver, else 0
|
|
*/
|
|
struct dma_tx_state {
|
|
dma_cookie_t last;
|
|
dma_cookie_t used;
|
|
u32 residue;
|
|
};
|
|
|
|
/**
|
|
* struct dma_device - info on the entity supplying DMA services
|
|
* @chancnt: how many DMA channels are supported
|
|
* @privatecnt: how many DMA channels are requested by dma_request_channel
|
|
* @channels: the list of struct dma_chan
|
|
* @global_node: list_head for global dma_device_list
|
|
* @cap_mask: one or more dma_capability flags
|
|
* @max_xor: maximum number of xor sources, 0 if no capability
|
|
* @max_pq: maximum number of PQ sources and PQ-continue capability
|
|
* @copy_align: alignment shift for memcpy operations
|
|
* @xor_align: alignment shift for xor operations
|
|
* @pq_align: alignment shift for pq operations
|
|
* @fill_align: alignment shift for memset operations
|
|
* @dev_id: unique device ID
|
|
* @dev: struct device reference for dma mapping api
|
|
* @device_alloc_chan_resources: allocate resources and return the
|
|
* number of allocated descriptors
|
|
* @device_free_chan_resources: release DMA channel's resources
|
|
* @device_prep_dma_memcpy: prepares a memcpy operation
|
|
* @device_prep_dma_xor: prepares a xor operation
|
|
* @device_prep_dma_xor_val: prepares a xor validation operation
|
|
* @device_prep_dma_pq: prepares a pq operation
|
|
* @device_prep_dma_pq_val: prepares a pqzero_sum operation
|
|
* @device_prep_dma_interrupt: prepares an end of chain interrupt operation
|
|
* @device_prep_slave_sg: prepares a slave dma operation
|
|
* @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
|
|
* The function takes a buffer of size buf_len. The callback function will
|
|
* be called after period_len bytes have been transferred.
|
|
* @device_prep_interleaved_dma: Transfer expression in a generic way.
|
|
* @device_control: manipulate all pending operations on a channel, returns
|
|
* zero or error code
|
|
* @device_tx_status: poll for transaction completion, the optional
|
|
* txstate parameter can be supplied with a pointer to get a
|
|
* struct with auxiliary transfer status information, otherwise the call
|
|
* will just return a simple status code
|
|
* @device_issue_pending: push pending transactions to hardware
|
|
* @device_slave_caps: return the slave channel capabilities
|
|
*/
|
|
struct dma_device {
|
|
|
|
unsigned int chancnt;
|
|
unsigned int privatecnt;
|
|
struct list_head channels;
|
|
struct list_head global_node;
|
|
dma_cap_mask_t cap_mask;
|
|
unsigned short max_xor;
|
|
unsigned short max_pq;
|
|
u8 copy_align;
|
|
u8 xor_align;
|
|
u8 pq_align;
|
|
u8 fill_align;
|
|
#define DMA_HAS_PQ_CONTINUE (1 << 15)
|
|
|
|
int dev_id;
|
|
struct device *dev;
|
|
|
|
int (*device_alloc_chan_resources)(struct dma_chan *chan);
|
|
void (*device_free_chan_resources)(struct dma_chan *chan);
|
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
|
|
struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
|
|
size_t len, unsigned long flags);
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
|
|
struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
|
|
unsigned int src_cnt, size_t len, unsigned long flags);
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
|
|
struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
|
|
size_t len, enum sum_check_flags *result, unsigned long flags);
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
|
|
struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
|
|
unsigned int src_cnt, const unsigned char *scf,
|
|
size_t len, unsigned long flags);
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
|
|
struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
|
|
unsigned int src_cnt, const unsigned char *scf, size_t len,
|
|
enum sum_check_flags *pqres, unsigned long flags);
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
|
|
struct dma_chan *chan, unsigned long flags);
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
|
|
struct dma_chan *chan,
|
|
struct scatterlist *dst_sg, unsigned int dst_nents,
|
|
struct scatterlist *src_sg, unsigned int src_nents,
|
|
unsigned long flags);
|
|
|
|
struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
|
|
struct dma_chan *chan, struct scatterlist *sgl,
|
|
unsigned int sg_len, enum dma_transfer_direction direction,
|
|
unsigned long flags, void *context);
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
|
|
struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
|
|
size_t period_len, enum dma_transfer_direction direction,
|
|
unsigned long flags, void *context);
|
|
struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
|
|
struct dma_chan *chan, struct dma_interleaved_template *xt,
|
|
unsigned long flags);
|
|
int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|
unsigned long arg);
|
|
|
|
enum dma_status (*device_tx_status)(struct dma_chan *chan,
|
|
dma_cookie_t cookie,
|
|
struct dma_tx_state *txstate);
|
|
void (*device_issue_pending)(struct dma_chan *chan);
|
|
int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
|
|
};
|
|
|
|
static inline int dmaengine_device_control(struct dma_chan *chan,
|
|
enum dma_ctrl_cmd cmd,
|
|
unsigned long arg)
|
|
{
|
|
if (chan->device->device_control)
|
|
return chan->device->device_control(chan, cmd, arg);
|
|
|
|
return -ENOSYS;
|
|
}
|
|
|
|
static inline int dmaengine_slave_config(struct dma_chan *chan,
|
|
struct dma_slave_config *config)
|
|
{
|
|
return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
|
|
(unsigned long)config);
|
|
}
|
|
|
|
static inline bool is_slave_direction(enum dma_transfer_direction direction)
|
|
{
|
|
return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
|
|
struct dma_chan *chan, dma_addr_t buf, size_t len,
|
|
enum dma_transfer_direction dir, unsigned long flags)
|
|
{
|
|
struct scatterlist sg;
|
|
sg_init_table(&sg, 1);
|
|
sg_dma_address(&sg) = buf;
|
|
sg_dma_len(&sg) = len;
|
|
|
|
return chan->device->device_prep_slave_sg(chan, &sg, 1,
|
|
dir, flags, NULL);
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
|
|
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
|
|
enum dma_transfer_direction dir, unsigned long flags)
|
|
{
|
|
return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
|
|
dir, flags, NULL);
|
|
}
|
|
|
|
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
|
struct rio_dma_ext;
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
|
|
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
|
|
enum dma_transfer_direction dir, unsigned long flags,
|
|
struct rio_dma_ext *rio_ext)
|
|
{
|
|
return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
|
|
dir, flags, rio_ext);
|
|
}
|
|
#endif
|
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
|
|
struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
|
|
size_t period_len, enum dma_transfer_direction dir,
|
|
unsigned long flags)
|
|
{
|
|
return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
|
|
period_len, dir, flags, NULL);
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
|
|
struct dma_chan *chan, struct dma_interleaved_template *xt,
|
|
unsigned long flags)
|
|
{
|
|
return chan->device->device_prep_interleaved_dma(chan, xt, flags);
|
|
}
|
|
|
|
static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
|
|
{
|
|
if (!chan || !caps)
|
|
return -EINVAL;
|
|
|
|
/* check if the channel supports slave transactions */
|
|
if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits))
|
|
return -ENXIO;
|
|
|
|
if (chan->device->device_slave_caps)
|
|
return chan->device->device_slave_caps(chan, caps);
|
|
|
|
return -ENXIO;
|
|
}
|
|
|
|
static inline int dmaengine_terminate_all(struct dma_chan *chan)
|
|
{
|
|
return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
|
|
}
|
|
|
|
static inline int dmaengine_pause(struct dma_chan *chan)
|
|
{
|
|
return dmaengine_device_control(chan, DMA_PAUSE, 0);
|
|
}
|
|
|
|
static inline int dmaengine_resume(struct dma_chan *chan)
|
|
{
|
|
return dmaengine_device_control(chan, DMA_RESUME, 0);
|
|
}
|
|
|
|
static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
|
|
dma_cookie_t cookie, struct dma_tx_state *state)
|
|
{
|
|
return chan->device->device_tx_status(chan, cookie, state);
|
|
}
|
|
|
|
static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
|
|
{
|
|
return desc->tx_submit(desc);
|
|
}
|
|
|
|
static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
|
|
{
|
|
size_t mask;
|
|
|
|
if (!align)
|
|
return true;
|
|
mask = (1 << align) - 1;
|
|
if (mask & (off1 | off2 | len))
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
|
|
size_t off2, size_t len)
|
|
{
|
|
return dmaengine_check_align(dev->copy_align, off1, off2, len);
|
|
}
|
|
|
|
static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
|
|
size_t off2, size_t len)
|
|
{
|
|
return dmaengine_check_align(dev->xor_align, off1, off2, len);
|
|
}
|
|
|
|
static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
|
|
size_t off2, size_t len)
|
|
{
|
|
return dmaengine_check_align(dev->pq_align, off1, off2, len);
|
|
}
|
|
|
|
static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
|
|
size_t off2, size_t len)
|
|
{
|
|
return dmaengine_check_align(dev->fill_align, off1, off2, len);
|
|
}
|
|
|
|
static inline void
|
|
dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
|
|
{
|
|
dma->max_pq = maxpq;
|
|
if (has_pq_continue)
|
|
dma->max_pq |= DMA_HAS_PQ_CONTINUE;
|
|
}
|
|
|
|
static inline bool dmaf_continue(enum dma_ctrl_flags flags)
|
|
{
|
|
return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
|
|
}
|
|
|
|
static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
|
|
{
|
|
enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
|
|
|
|
return (flags & mask) == mask;
|
|
}
|
|
|
|
static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
|
|
{
|
|
return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
|
|
}
|
|
|
|
static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
|
|
{
|
|
return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
|
|
}
|
|
|
|
/* dma_maxpq - reduce maxpq in the face of continued operations
|
|
* @dma - dma device with PQ capability
|
|
* @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
|
|
*
|
|
* When an engine does not support native continuation we need 3 extra
|
|
* source slots to reuse P and Q with the following coefficients:
|
|
* 1/ {00} * P : remove P from Q', but use it as a source for P'
|
|
* 2/ {01} * Q : use Q to continue Q' calculation
|
|
* 3/ {00} * Q : subtract Q from P' to cancel (2)
|
|
*
|
|
* In the case where P is disabled we only need 1 extra source:
|
|
* 1/ {01} * Q : use Q to continue Q' calculation
|
|
*/
|
|
static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
|
|
{
|
|
if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
|
|
return dma_dev_to_maxpq(dma);
|
|
else if (dmaf_p_disabled_continue(flags))
|
|
return dma_dev_to_maxpq(dma) - 1;
|
|
else if (dmaf_continue(flags))
|
|
return dma_dev_to_maxpq(dma) - 3;
|
|
BUG();
|
|
}
|
|
|
|
/* --- public DMA engine API --- */
|
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
|
void dmaengine_get(void);
|
|
void dmaengine_put(void);
|
|
#else
|
|
static inline void dmaengine_get(void)
|
|
{
|
|
}
|
|
static inline void dmaengine_put(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_NET_DMA
|
|
#define net_dmaengine_get() dmaengine_get()
|
|
#define net_dmaengine_put() dmaengine_put()
|
|
#else
|
|
static inline void net_dmaengine_get(void)
|
|
{
|
|
}
|
|
static inline void net_dmaengine_put(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ASYNC_TX_DMA
|
|
#define async_dmaengine_get() dmaengine_get()
|
|
#define async_dmaengine_put() dmaengine_put()
|
|
#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
|
#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
|
|
#else
|
|
#define async_dma_find_channel(type) dma_find_channel(type)
|
|
#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
|
|
#else
|
|
static inline void async_dmaengine_get(void)
|
|
{
|
|
}
|
|
static inline void async_dmaengine_put(void)
|
|
{
|
|
}
|
|
static inline struct dma_chan *
|
|
async_dma_find_channel(enum dma_transaction_type type)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif /* CONFIG_ASYNC_TX_DMA */
|
|
|
|
dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
|
|
void *dest, void *src, size_t len);
|
|
dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
|
|
struct page *page, unsigned int offset, void *kdata, size_t len);
|
|
dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
|
|
struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
|
|
unsigned int src_off, size_t len);
|
|
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
|
|
struct dma_chan *chan);
|
|
|
|
static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
tx->flags |= DMA_CTRL_ACK;
|
|
}
|
|
|
|
static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
tx->flags &= ~DMA_CTRL_ACK;
|
|
}
|
|
|
|
static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
|
|
}
|
|
|
|
#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
|
|
static inline void
|
|
__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
|
|
{
|
|
set_bit(tx_type, dstp->bits);
|
|
}
|
|
|
|
#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
|
|
static inline void
|
|
__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
|
|
{
|
|
clear_bit(tx_type, dstp->bits);
|
|
}
|
|
|
|
#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
|
|
static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
|
|
{
|
|
bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
|
|
}
|
|
|
|
#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
|
|
static inline int
|
|
__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
|
|
{
|
|
return test_bit(tx_type, srcp->bits);
|
|
}
|
|
|
|
#define for_each_dma_cap_mask(cap, mask) \
|
|
for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
|
|
|
|
/**
|
|
* dma_async_issue_pending - flush pending transactions to HW
|
|
* @chan: target DMA channel
|
|
*
|
|
* This allows drivers to push copies to HW in batches,
|
|
* reducing MMIO writes where possible.
|
|
*/
|
|
static inline void dma_async_issue_pending(struct dma_chan *chan)
|
|
{
|
|
chan->device->device_issue_pending(chan);
|
|
}
|
|
|
|
/**
|
|
* dma_async_is_tx_complete - poll for transaction completion
|
|
* @chan: DMA channel
|
|
* @cookie: transaction identifier to check status of
|
|
* @last: returns last completed cookie, can be NULL
|
|
* @used: returns last issued cookie, can be NULL
|
|
*
|
|
* If @last and @used are passed in, upon return they reflect the driver
|
|
* internal state and can be used with dma_async_is_complete() to check
|
|
* the status of multiple cookies without re-checking hardware state.
|
|
*/
|
|
static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
|
|
dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
|
|
{
|
|
struct dma_tx_state state;
|
|
enum dma_status status;
|
|
|
|
status = chan->device->device_tx_status(chan, cookie, &state);
|
|
if (last)
|
|
*last = state.last;
|
|
if (used)
|
|
*used = state.used;
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* dma_async_is_complete - test a cookie against chan state
|
|
* @cookie: transaction identifier to test status of
|
|
* @last_complete: last know completed transaction
|
|
* @last_used: last cookie value handed out
|
|
*
|
|
* dma_async_is_complete() is used in dma_async_is_tx_complete()
|
|
* the test logic is separated for lightweight testing of multiple cookies
|
|
*/
|
|
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
|
|
dma_cookie_t last_complete, dma_cookie_t last_used)
|
|
{
|
|
if (last_complete <= last_used) {
|
|
if ((cookie <= last_complete) || (cookie > last_used))
|
|
return DMA_SUCCESS;
|
|
} else {
|
|
if ((cookie <= last_complete) && (cookie > last_used))
|
|
return DMA_SUCCESS;
|
|
}
|
|
return DMA_IN_PROGRESS;
|
|
}
|
|
|
|
static inline void
|
|
dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
|
|
{
|
|
if (st) {
|
|
st->last = last;
|
|
st->used = used;
|
|
st->residue = residue;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
|
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
|
|
enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
|
|
enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
|
|
void dma_issue_pending_all(void);
|
|
struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
|
|
dma_filter_fn fn, void *fn_param);
|
|
struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
|
|
void dma_release_channel(struct dma_chan *chan);
|
|
#else
|
|
static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
|
|
{
|
|
return NULL;
|
|
}
|
|
static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
|
|
{
|
|
return DMA_SUCCESS;
|
|
}
|
|
static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
return DMA_SUCCESS;
|
|
}
|
|
static inline void dma_issue_pending_all(void)
|
|
{
|
|
}
|
|
static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
|
|
dma_filter_fn fn, void *fn_param)
|
|
{
|
|
return NULL;
|
|
}
|
|
static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
|
|
const char *name)
|
|
{
|
|
return NULL;
|
|
}
|
|
static inline void dma_release_channel(struct dma_chan *chan)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/* --- DMA device --- */
|
|
|
|
int dma_async_device_register(struct dma_device *device);
|
|
void dma_async_device_unregister(struct dma_device *device);
|
|
void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
|
|
struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
|
|
struct dma_chan *net_dma_find_channel(void);
|
|
#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
|
|
#define dma_request_slave_channel_compat(mask, x, y, dev, name) \
|
|
__dma_request_slave_channel_compat(&(mask), x, y, dev, name)
|
|
|
|
static inline struct dma_chan
|
|
*__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
|
|
dma_filter_fn fn, void *fn_param,
|
|
struct device *dev, char *name)
|
|
{
|
|
struct dma_chan *chan;
|
|
|
|
chan = dma_request_slave_channel(dev, name);
|
|
if (chan)
|
|
return chan;
|
|
|
|
return __dma_request_channel(mask, fn, fn_param);
|
|
}
|
|
|
|
/* --- Helper iov-locking functions --- */
|
|
|
|
struct dma_page_list {
|
|
char __user *base_address;
|
|
int nr_pages;
|
|
struct page **pages;
|
|
};
|
|
|
|
struct dma_pinned_list {
|
|
int nr_iovecs;
|
|
struct dma_page_list page_list[0];
|
|
};
|
|
|
|
struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
|
|
void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
|
|
|
|
dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
|
|
struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
|
|
dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
|
|
struct dma_pinned_list *pinned_list, struct page *page,
|
|
unsigned int offset, size_t len);
|
|
|
|
#endif /* DMAENGINE_H */
|