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4a6369e993
This adds dpm support for rv6xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: remove duplicate line v3: fix thermal interrupt check noticed by Jerome Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
95 lines
2.5 KiB
C
95 lines
2.5 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef __RV6XX_DPM_H__
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#define __RV6XX_DPM_H__
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#include "r600_dpm.h"
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/* Represents a single SCLK step. */
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struct rv6xx_sclk_stepping
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{
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u32 vco_frequency;
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u32 post_divider;
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};
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struct rv6xx_pm_hw_state {
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u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
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u32 mclks[R600_PM_NUMBER_OF_MCLKS];
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u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
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bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];
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bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
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u8 high_sclk_index;
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u8 medium_sclk_index;
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u8 low_sclk_index;
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u8 high_mclk_index;
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u8 medium_mclk_index;
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u8 low_mclk_index;
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u8 high_vddc_index;
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u8 medium_vddc_index;
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u8 low_vddc_index;
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u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
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u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];
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};
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struct rv6xx_power_info {
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/* flags */
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bool voltage_control;
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bool sclk_ss;
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bool mclk_ss;
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bool dynamic_ss;
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bool dynamic_pcie_gen2;
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bool thermal_protection;
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bool display_gap;
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bool gfx_clock_gating;
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/* clk values */
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u32 fb_div_scale;
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u32 spll_ref_div;
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u32 mpll_ref_div;
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u32 bsu;
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u32 bsp;
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/* */
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u32 active_auto_throttle_sources;
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/* current power state */
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u32 restricted_levels;
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struct rv6xx_pm_hw_state hw;
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};
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struct rv6xx_pl {
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u32 sclk;
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u32 mclk;
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u16 vddc;
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u32 flags;
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};
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struct rv6xx_ps {
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struct rv6xx_pl high;
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struct rv6xx_pl medium;
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struct rv6xx_pl low;
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};
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#define RV6XX_DEFAULT_VCLK_FREQ 40000 /* 10 khz */
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#define RV6XX_DEFAULT_DCLK_FREQ 30000 /* 10 khz */
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#endif
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