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f88c5ee774
Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
157 lines
5 KiB
C
157 lines
5 KiB
C
/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef _SUN8I_MIXER_H_
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#define _SUN8I_MIXER_H_
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "sun8i_csc.h"
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#include "sunxi_engine.h"
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#define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
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#define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x))
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#define SUN8I_MIXER_GLOBAL_CTL 0x0
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#define SUN8I_MIXER_GLOBAL_STATUS 0x4
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#define SUN8I_MIXER_GLOBAL_DBUFF 0x8
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#define SUN8I_MIXER_GLOBAL_SIZE 0xc
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#define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
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#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
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#define SUN8I_MIXER_BLEND_PIPE_CTL 0x1000
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#define SUN8I_MIXER_BLEND_ATTR_FCOLOR(x) (0x1004 + 0x10 * (x) + 0x0)
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#define SUN8I_MIXER_BLEND_ATTR_INSIZE(x) (0x1004 + 0x10 * (x) + 0x4)
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#define SUN8I_MIXER_BLEND_ATTR_COORD(x) (0x1004 + 0x10 * (x) + 0x8)
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#define SUN8I_MIXER_BLEND_ROUTE 0x1080
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#define SUN8I_MIXER_BLEND_PREMULTIPLY 0x1084
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#define SUN8I_MIXER_BLEND_BKCOLOR 0x1088
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#define SUN8I_MIXER_BLEND_OUTSIZE 0x108c
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#define SUN8I_MIXER_BLEND_MODE(x) (0x1090 + 0x04 * (x))
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#define SUN8I_MIXER_BLEND_CK_CTL 0x10b0
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#define SUN8I_MIXER_BLEND_CK_CFG 0x10b4
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#define SUN8I_MIXER_BLEND_CK_MAX(x) (0x10c0 + 0x04 * (x))
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#define SUN8I_MIXER_BLEND_CK_MIN(x) (0x10e0 + 0x04 * (x))
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#define SUN8I_MIXER_BLEND_OUTCTL 0x10fc
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#define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK GENMASK(12, 8)
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#define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
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#define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe)
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/* colors are always in AARRGGBB format */
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#define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000
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/* The following numbers are some still unknown magic numbers */
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#define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301
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#define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2))
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#define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n) ((n) << 2)
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#define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
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#define SUN8I_MIXER_FBFMT_ARGB8888 0
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#define SUN8I_MIXER_FBFMT_ABGR8888 1
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#define SUN8I_MIXER_FBFMT_RGBA8888 2
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#define SUN8I_MIXER_FBFMT_BGRA8888 3
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#define SUN8I_MIXER_FBFMT_XRGB8888 4
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#define SUN8I_MIXER_FBFMT_XBGR8888 5
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#define SUN8I_MIXER_FBFMT_RGBX8888 6
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#define SUN8I_MIXER_FBFMT_BGRX8888 7
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#define SUN8I_MIXER_FBFMT_RGB888 8
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#define SUN8I_MIXER_FBFMT_BGR888 9
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#define SUN8I_MIXER_FBFMT_RGB565 10
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#define SUN8I_MIXER_FBFMT_BGR565 11
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#define SUN8I_MIXER_FBFMT_ARGB4444 12
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#define SUN8I_MIXER_FBFMT_ABGR4444 13
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#define SUN8I_MIXER_FBFMT_RGBA4444 14
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#define SUN8I_MIXER_FBFMT_BGRA4444 15
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#define SUN8I_MIXER_FBFMT_ARGB1555 16
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#define SUN8I_MIXER_FBFMT_ABGR1555 17
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#define SUN8I_MIXER_FBFMT_RGBA5551 18
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#define SUN8I_MIXER_FBFMT_BGRA5551 19
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#define SUN8I_MIXER_FBFMT_YUYV 0
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#define SUN8I_MIXER_FBFMT_UYVY 1
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#define SUN8I_MIXER_FBFMT_YVYU 2
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#define SUN8I_MIXER_FBFMT_VYUY 3
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#define SUN8I_MIXER_FBFMT_NV16 4
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#define SUN8I_MIXER_FBFMT_NV61 5
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#define SUN8I_MIXER_FBFMT_YUV422 6
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/* format 7 doesn't exist */
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#define SUN8I_MIXER_FBFMT_NV12 8
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#define SUN8I_MIXER_FBFMT_NV21 9
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#define SUN8I_MIXER_FBFMT_YUV420 10
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/* format 11 doesn't exist */
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/* format 12 is semi-planar YUV411 UVUV */
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/* format 13 is semi-planar YUV411 VUVU */
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#define SUN8I_MIXER_FBFMT_YUV411 14
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/*
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* These sub-engines are still unknown now, the EN registers are here only to
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* be used to disable these sub-engines.
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*/
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#define SUN8I_MIXER_FCE_EN 0xa0000
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#define SUN8I_MIXER_BWS_EN 0xa2000
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#define SUN8I_MIXER_LTI_EN 0xa4000
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#define SUN8I_MIXER_PEAK_EN 0xa6000
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#define SUN8I_MIXER_ASE_EN 0xa8000
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#define SUN8I_MIXER_FCC_EN 0xaa000
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#define SUN8I_MIXER_DCSC_EN 0xb0000
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struct de2_fmt_info {
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u32 drm_fmt;
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u32 de2_fmt;
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bool rgb;
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enum sun8i_csc_mode csc;
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};
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/**
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* struct sun8i_mixer_cfg - mixer HW configuration
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* @vi_num: number of VI channels
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* @ui_num: number of UI channels
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* @scaler_mask: bitmask which tells which channel supports scaling
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* First, scaler supports for VI channels is defined and after that, scaler
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* support for UI channels. For example, if mixer has 2 VI channels without
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* scaler and 2 UI channels with scaler, bitmask would be 0xC.
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* @ccsc: select set of CCSC base addresses
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* Set value to 0 if this is first mixer or second mixer with VEP support.
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* Set value to 1 if this is second mixer without VEP support. Other values
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* are invalid.
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* @mod_rate: module clock rate that needs to be set in order to have
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* a functional block.
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*/
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struct sun8i_mixer_cfg {
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int vi_num;
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int ui_num;
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int scaler_mask;
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int ccsc;
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unsigned long mod_rate;
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};
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struct sun8i_mixer {
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struct sunxi_engine engine;
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const struct sun8i_mixer_cfg *cfg;
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struct reset_control *reset;
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struct clk *bus_clk;
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struct clk *mod_clk;
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};
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static inline struct sun8i_mixer *
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engine_to_sun8i_mixer(struct sunxi_engine *engine)
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{
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return container_of(engine, struct sun8i_mixer, engine);
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}
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const struct de2_fmt_info *sun8i_mixer_format_info(u32 format);
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#endif /* _SUN8I_MIXER_H_ */
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