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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-31 16:38:12 +00:00
763 lines
23 KiB
C
763 lines
23 KiB
C
/*
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* System-specific setup, especially interrupts.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1998 Harald Koerfgen
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* Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
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*/
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#include <linux/console.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/param.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/pm.h>
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#include <asm/bootinfo.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/traps.h>
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#include <asm/wbflush.h>
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#include <asm/dec/interrupts.h>
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#include <asm/dec/ioasic.h>
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#include <asm/dec/ioasic_addrs.h>
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#include <asm/dec/ioasic_ints.h>
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#include <asm/dec/kn01.h>
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#include <asm/dec/kn02.h>
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#include <asm/dec/kn02ba.h>
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#include <asm/dec/kn02ca.h>
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#include <asm/dec/kn03.h>
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#include <asm/dec/kn230.h>
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#include <asm/dec/system.h>
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extern void dec_machine_restart(char *command);
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extern void dec_machine_halt(void);
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extern void dec_machine_power_off(void);
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extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
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unsigned long dec_kn_slot_base, dec_kn_slot_size;
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EXPORT_SYMBOL(dec_kn_slot_base);
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EXPORT_SYMBOL(dec_kn_slot_size);
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spinlock_t ioasic_ssr_lock;
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volatile u32 *ioasic_base;
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EXPORT_SYMBOL(ioasic_base);
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/*
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* IRQ routing and priority tables. Priorites are set as follows:
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*
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* KN01 KN230 KN02 KN02-BA KN02-CA KN03
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*
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* MEMORY CPU CPU CPU ASIC CPU CPU
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* RTC CPU CPU CPU ASIC CPU CPU
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* DMA - - - ASIC ASIC ASIC
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* SERIAL0 CPU CPU CSR ASIC ASIC ASIC
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* SERIAL1 - - - ASIC - ASIC
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* SCSI CPU CPU CSR ASIC ASIC ASIC
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* ETHERNET CPU * CSR ASIC ASIC ASIC
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* other - - - ASIC - -
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* TC2 - - CSR CPU ASIC ASIC
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* TC1 - - CSR CPU ASIC ASIC
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* TC0 - - CSR CPU ASIC ASIC
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* other - CPU - CPU ASIC ASIC
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* other - - - - CPU CPU
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*
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* * -- shared with SCSI
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*/
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int dec_interrupt[DEC_NR_INTS] = {
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[0 ... DEC_NR_INTS - 1] = -1
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};
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EXPORT_SYMBOL(dec_interrupt);
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int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
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{ { .i = ~0 }, { .p = dec_intr_unimplemented } },
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};
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int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
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{ { .i = ~0 }, { .p = asic_intr_unimplemented } },
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};
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int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
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static struct irqaction ioirq = {
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.handler = no_action,
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.name = "cascade",
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};
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static struct irqaction fpuirq = {
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.handler = no_action,
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.name = "fpu",
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};
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static struct irqaction busirq = {
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.flags = IRQF_DISABLED,
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.name = "bus error",
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};
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static struct irqaction haltirq = {
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.handler = dec_intr_halt,
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.name = "halt",
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};
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/*
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* Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
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*/
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static void __init dec_be_init(void)
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{
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switch (mips_machtype) {
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case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
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board_be_handler = dec_kn01_be_handler;
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busirq.handler = dec_kn01_be_interrupt;
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busirq.flags |= IRQF_SHARED;
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dec_kn01_be_init();
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break;
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case MACH_DS5000_1XX: /* DS5000/1xx 3min */
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case MACH_DS5000_XX: /* DS5000/xx Maxine */
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board_be_handler = dec_kn02xa_be_handler;
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busirq.handler = dec_kn02xa_be_interrupt;
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dec_kn02xa_be_init();
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break;
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case MACH_DS5000_200: /* DS5000/200 3max */
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case MACH_DS5000_2X0: /* DS5000/240 3max+ */
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case MACH_DS5900: /* DS5900 bigmax */
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board_be_handler = dec_ecc_be_handler;
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busirq.handler = dec_ecc_be_interrupt;
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dec_ecc_be_init();
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break;
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}
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}
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extern void dec_time_init(void);
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void __init plat_mem_setup(void)
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{
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board_be_init = dec_be_init;
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board_time_init = dec_time_init;
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wbflush_setup();
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_machine_restart = dec_machine_restart;
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_machine_halt = dec_machine_halt;
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pm_power_off = dec_machine_power_off;
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ioport_resource.start = ~0UL;
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ioport_resource.end = 0UL;
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}
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/*
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* Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
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* or DS3100 (aka Pmax).
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*/
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static int kn01_interrupt[DEC_NR_INTS] __initdata = {
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[DEC_IRQ_CASCADE] = -1,
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[DEC_IRQ_AB_RECV] = -1,
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[DEC_IRQ_AB_XMIT] = -1,
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[DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
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[DEC_IRQ_ASC] = -1,
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[DEC_IRQ_FLOPPY] = -1,
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[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
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[DEC_IRQ_HALT] = -1,
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[DEC_IRQ_ISDN] = -1,
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[DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
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[DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
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[DEC_IRQ_PSU] = -1,
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[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
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[DEC_IRQ_SCC0] = -1,
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[DEC_IRQ_SCC1] = -1,
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[DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
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[DEC_IRQ_TC0] = -1,
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[DEC_IRQ_TC1] = -1,
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[DEC_IRQ_TC2] = -1,
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[DEC_IRQ_TIMER] = -1,
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[DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
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[DEC_IRQ_ASC_MERR] = -1,
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[DEC_IRQ_ASC_ERR] = -1,
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[DEC_IRQ_ASC_DMA] = -1,
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[DEC_IRQ_FLOPPY_ERR] = -1,
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[DEC_IRQ_ISDN_ERR] = -1,
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[DEC_IRQ_ISDN_RXDMA] = -1,
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[DEC_IRQ_ISDN_TXDMA] = -1,
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[DEC_IRQ_LANCE_MERR] = -1,
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[DEC_IRQ_SCC0A_RXERR] = -1,
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[DEC_IRQ_SCC0A_RXDMA] = -1,
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[DEC_IRQ_SCC0A_TXERR] = -1,
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[DEC_IRQ_SCC0A_TXDMA] = -1,
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[DEC_IRQ_AB_RXERR] = -1,
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[DEC_IRQ_AB_RXDMA] = -1,
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[DEC_IRQ_AB_TXERR] = -1,
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[DEC_IRQ_AB_TXDMA] = -1,
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[DEC_IRQ_SCC1A_RXERR] = -1,
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[DEC_IRQ_SCC1A_RXDMA] = -1,
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[DEC_IRQ_SCC1A_TXERR] = -1,
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[DEC_IRQ_SCC1A_TXDMA] = -1,
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};
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static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
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{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
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{ .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
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{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
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{ .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
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{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
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{ .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
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{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
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{ .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
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{ { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
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{ .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
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{ { .i = DEC_CPU_IRQ_ALL },
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{ .p = cpu_all_int } },
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};
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static void __init dec_init_kn01(void)
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{
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/* IRQ routing. */
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memcpy(&dec_interrupt, &kn01_interrupt,
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sizeof(kn01_interrupt));
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/* CPU IRQ priorities. */
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memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
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sizeof(kn01_cpu_mask_nr_tbl));
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mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
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} /* dec_init_kn01 */
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/*
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* Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
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*/
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static int kn230_interrupt[DEC_NR_INTS] __initdata = {
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[DEC_IRQ_CASCADE] = -1,
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[DEC_IRQ_AB_RECV] = -1,
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[DEC_IRQ_AB_XMIT] = -1,
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[DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
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[DEC_IRQ_ASC] = -1,
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[DEC_IRQ_FLOPPY] = -1,
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[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
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[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
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[DEC_IRQ_ISDN] = -1,
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[DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
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[DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
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[DEC_IRQ_PSU] = -1,
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[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
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[DEC_IRQ_SCC0] = -1,
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[DEC_IRQ_SCC1] = -1,
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[DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
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[DEC_IRQ_TC0] = -1,
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[DEC_IRQ_TC1] = -1,
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[DEC_IRQ_TC2] = -1,
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[DEC_IRQ_TIMER] = -1,
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[DEC_IRQ_VIDEO] = -1,
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[DEC_IRQ_ASC_MERR] = -1,
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[DEC_IRQ_ASC_ERR] = -1,
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[DEC_IRQ_ASC_DMA] = -1,
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[DEC_IRQ_FLOPPY_ERR] = -1,
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[DEC_IRQ_ISDN_ERR] = -1,
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[DEC_IRQ_ISDN_RXDMA] = -1,
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[DEC_IRQ_ISDN_TXDMA] = -1,
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[DEC_IRQ_LANCE_MERR] = -1,
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[DEC_IRQ_SCC0A_RXERR] = -1,
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[DEC_IRQ_SCC0A_RXDMA] = -1,
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[DEC_IRQ_SCC0A_TXERR] = -1,
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[DEC_IRQ_SCC0A_TXDMA] = -1,
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[DEC_IRQ_AB_RXERR] = -1,
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[DEC_IRQ_AB_RXDMA] = -1,
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[DEC_IRQ_AB_TXERR] = -1,
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[DEC_IRQ_AB_TXDMA] = -1,
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[DEC_IRQ_SCC1A_RXERR] = -1,
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[DEC_IRQ_SCC1A_RXDMA] = -1,
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[DEC_IRQ_SCC1A_TXERR] = -1,
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[DEC_IRQ_SCC1A_TXDMA] = -1,
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};
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static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
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{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
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{ .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
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{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
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{ .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
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{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
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{ .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
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{ { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
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{ .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
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{ { .i = DEC_CPU_IRQ_ALL },
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{ .p = cpu_all_int } },
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};
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static void __init dec_init_kn230(void)
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{
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/* IRQ routing. */
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memcpy(&dec_interrupt, &kn230_interrupt,
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sizeof(kn230_interrupt));
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/* CPU IRQ priorities. */
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memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
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sizeof(kn230_cpu_mask_nr_tbl));
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mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
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} /* dec_init_kn230 */
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/*
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* Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
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*/
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static int kn02_interrupt[DEC_NR_INTS] __initdata = {
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[DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
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[DEC_IRQ_AB_RECV] = -1,
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[DEC_IRQ_AB_XMIT] = -1,
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[DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
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[DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC),
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[DEC_IRQ_FLOPPY] = -1,
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[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
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[DEC_IRQ_HALT] = -1,
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[DEC_IRQ_ISDN] = -1,
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[DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
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[DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
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[DEC_IRQ_PSU] = -1,
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[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
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[DEC_IRQ_SCC0] = -1,
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[DEC_IRQ_SCC1] = -1,
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[DEC_IRQ_SII] = -1,
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[DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0),
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[DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1),
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[DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2),
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[DEC_IRQ_TIMER] = -1,
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[DEC_IRQ_VIDEO] = -1,
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[DEC_IRQ_ASC_MERR] = -1,
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[DEC_IRQ_ASC_ERR] = -1,
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[DEC_IRQ_ASC_DMA] = -1,
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[DEC_IRQ_FLOPPY_ERR] = -1,
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[DEC_IRQ_ISDN_ERR] = -1,
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[DEC_IRQ_ISDN_RXDMA] = -1,
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[DEC_IRQ_ISDN_TXDMA] = -1,
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[DEC_IRQ_LANCE_MERR] = -1,
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[DEC_IRQ_SCC0A_RXERR] = -1,
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[DEC_IRQ_SCC0A_RXDMA] = -1,
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[DEC_IRQ_SCC0A_TXERR] = -1,
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[DEC_IRQ_SCC0A_TXDMA] = -1,
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[DEC_IRQ_AB_RXERR] = -1,
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[DEC_IRQ_AB_RXDMA] = -1,
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[DEC_IRQ_AB_TXERR] = -1,
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[DEC_IRQ_AB_TXDMA] = -1,
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[DEC_IRQ_SCC1A_RXERR] = -1,
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[DEC_IRQ_SCC1A_RXDMA] = -1,
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[DEC_IRQ_SCC1A_TXERR] = -1,
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[DEC_IRQ_SCC1A_TXDMA] = -1,
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};
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static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
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{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
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{ .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
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{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
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{ .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
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{ { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
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{ .p = kn02_io_int } },
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{ { .i = DEC_CPU_IRQ_ALL },
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{ .p = cpu_all_int } },
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};
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static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
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{ { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
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{ .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
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{ { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
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{ .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
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{ { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
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{ .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
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{ { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
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{ .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
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{ { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
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{ .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
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{ { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
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{ .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
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{ { .i = KN02_IRQ_ALL },
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{ .p = kn02_all_int } },
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};
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static void __init dec_init_kn02(void)
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{
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/* IRQ routing. */
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memcpy(&dec_interrupt, &kn02_interrupt,
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sizeof(kn02_interrupt));
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/* CPU IRQ priorities. */
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memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
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sizeof(kn02_cpu_mask_nr_tbl));
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|
|
|
/* KN02 CSR IRQ priorities. */
|
|
memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
|
|
sizeof(kn02_asic_mask_nr_tbl));
|
|
|
|
mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
|
|
init_kn02_irqs(KN02_IRQ_BASE);
|
|
|
|
} /* dec_init_kn02 */
|
|
|
|
|
|
/*
|
|
* Machine-specific initialisation for KN02-BA, aka DS5000/1xx
|
|
* (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
|
|
* DS5000/150, aka 4min.
|
|
*/
|
|
static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
|
|
[DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
|
|
[DEC_IRQ_AB_RECV] = -1,
|
|
[DEC_IRQ_AB_XMIT] = -1,
|
|
[DEC_IRQ_DZ11] = -1,
|
|
[DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC),
|
|
[DEC_IRQ_FLOPPY] = -1,
|
|
[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
|
|
[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
|
|
[DEC_IRQ_ISDN] = -1,
|
|
[DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
|
|
[DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS),
|
|
[DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU),
|
|
[DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC),
|
|
[DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
|
|
[DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
|
|
[DEC_IRQ_SII] = -1,
|
|
[DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
|
|
[DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
|
|
[DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
|
|
[DEC_IRQ_TIMER] = -1,
|
|
[DEC_IRQ_VIDEO] = -1,
|
|
[DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
|
|
[DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
|
|
[DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
|
|
[DEC_IRQ_FLOPPY_ERR] = -1,
|
|
[DEC_IRQ_ISDN_ERR] = -1,
|
|
[DEC_IRQ_ISDN_RXDMA] = -1,
|
|
[DEC_IRQ_ISDN_TXDMA] = -1,
|
|
[DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
|
|
[DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
|
|
[DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
|
|
[DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
|
|
[DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
|
|
[DEC_IRQ_AB_RXERR] = -1,
|
|
[DEC_IRQ_AB_RXDMA] = -1,
|
|
[DEC_IRQ_AB_TXERR] = -1,
|
|
[DEC_IRQ_AB_TXDMA] = -1,
|
|
[DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
|
|
[DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
|
|
[DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
|
|
[DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
|
|
};
|
|
|
|
static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
|
|
{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
|
|
{ .p = kn02xa_io_int } },
|
|
{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
|
|
{ .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
|
|
{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
|
|
{ .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
|
|
{ { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
|
|
{ .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
|
|
{ { .i = DEC_CPU_IRQ_ALL },
|
|
{ .p = cpu_all_int } },
|
|
};
|
|
|
|
static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
|
|
{ { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
|
|
{ .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
|
|
{ { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
|
|
{ .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
|
|
{ { .i = IO_IRQ_DMA },
|
|
{ .p = asic_dma_int } },
|
|
{ { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
|
|
{ .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
|
|
{ { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
|
|
{ .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
|
|
{ { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
|
|
{ .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
|
|
{ { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
|
|
{ .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
|
|
{ { .i = IO_IRQ_ALL },
|
|
{ .p = asic_all_int } },
|
|
};
|
|
|
|
static void __init dec_init_kn02ba(void)
|
|
{
|
|
/* IRQ routing. */
|
|
memcpy(&dec_interrupt, &kn02ba_interrupt,
|
|
sizeof(kn02ba_interrupt));
|
|
|
|
/* CPU IRQ priorities. */
|
|
memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
|
|
sizeof(kn02ba_cpu_mask_nr_tbl));
|
|
|
|
/* I/O ASIC IRQ priorities. */
|
|
memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
|
|
sizeof(kn02ba_asic_mask_nr_tbl));
|
|
|
|
mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
|
|
init_ioasic_irqs(IO_IRQ_BASE);
|
|
|
|
} /* dec_init_kn02ba */
|
|
|
|
|
|
/*
|
|
* Machine-specific initialisation for KN02-CA, aka DS5000/xx,
|
|
* (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka
|
|
* DS5000/50, aka 4MAXine.
|
|
*/
|
|
static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
|
|
[DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
|
|
[DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
|
|
[DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
|
|
[DEC_IRQ_DZ11] = -1,
|
|
[DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC),
|
|
[DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
|
|
[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
|
|
[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
|
|
[DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
|
|
[DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
|
|
[DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
|
|
[DEC_IRQ_PSU] = -1,
|
|
[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
|
|
[DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
|
|
[DEC_IRQ_SCC1] = -1,
|
|
[DEC_IRQ_SII] = -1,
|
|
[DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0),
|
|
[DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1),
|
|
[DEC_IRQ_TC2] = -1,
|
|
[DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
|
|
[DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
|
|
[DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
|
|
[DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
|
|
[DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
|
|
[DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
|
|
[DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR),
|
|
[DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
|
|
[DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
|
|
[DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
|
|
[DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
|
|
[DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
|
|
[DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
|
|
[DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
|
|
[DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR),
|
|
[DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA),
|
|
[DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR),
|
|
[DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA),
|
|
[DEC_IRQ_SCC1A_RXERR] = -1,
|
|
[DEC_IRQ_SCC1A_RXDMA] = -1,
|
|
[DEC_IRQ_SCC1A_TXERR] = -1,
|
|
[DEC_IRQ_SCC1A_TXDMA] = -1,
|
|
};
|
|
|
|
static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
|
|
{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
|
|
{ .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
|
|
{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
|
|
{ .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
|
|
{ { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
|
|
{ .p = kn02xa_io_int } },
|
|
{ { .i = DEC_CPU_IRQ_ALL },
|
|
{ .p = cpu_all_int } },
|
|
};
|
|
|
|
static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
|
|
{ { .i = IO_IRQ_DMA },
|
|
{ .p = asic_dma_int } },
|
|
{ { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
|
|
{ .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
|
|
{ { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
|
|
{ .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
|
|
{ { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
|
|
{ .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
|
|
{ { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
|
|
{ .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
|
|
{ { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
|
|
{ .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
|
|
{ { .i = IO_IRQ_ALL },
|
|
{ .p = asic_all_int } },
|
|
};
|
|
|
|
static void __init dec_init_kn02ca(void)
|
|
{
|
|
/* IRQ routing. */
|
|
memcpy(&dec_interrupt, &kn02ca_interrupt,
|
|
sizeof(kn02ca_interrupt));
|
|
|
|
/* CPU IRQ priorities. */
|
|
memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
|
|
sizeof(kn02ca_cpu_mask_nr_tbl));
|
|
|
|
/* I/O ASIC IRQ priorities. */
|
|
memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
|
|
sizeof(kn02ca_asic_mask_nr_tbl));
|
|
|
|
mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
|
|
init_ioasic_irqs(IO_IRQ_BASE);
|
|
|
|
} /* dec_init_kn02ca */
|
|
|
|
|
|
/*
|
|
* Machine-specific initialisation for KN03, aka DS5000/240,
|
|
* aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka
|
|
* DS5000/260, aka 4max+ and DS5900/260.
|
|
*/
|
|
static int kn03_interrupt[DEC_NR_INTS] __initdata = {
|
|
[DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
|
|
[DEC_IRQ_AB_RECV] = -1,
|
|
[DEC_IRQ_AB_XMIT] = -1,
|
|
[DEC_IRQ_DZ11] = -1,
|
|
[DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC),
|
|
[DEC_IRQ_FLOPPY] = -1,
|
|
[DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
|
|
[DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
|
|
[DEC_IRQ_ISDN] = -1,
|
|
[DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE),
|
|
[DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
|
|
[DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU),
|
|
[DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
|
|
[DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0),
|
|
[DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1),
|
|
[DEC_IRQ_SII] = -1,
|
|
[DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0),
|
|
[DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1),
|
|
[DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2),
|
|
[DEC_IRQ_TIMER] = -1,
|
|
[DEC_IRQ_VIDEO] = -1,
|
|
[DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
|
|
[DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
|
|
[DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
|
|
[DEC_IRQ_FLOPPY_ERR] = -1,
|
|
[DEC_IRQ_ISDN_ERR] = -1,
|
|
[DEC_IRQ_ISDN_RXDMA] = -1,
|
|
[DEC_IRQ_ISDN_TXDMA] = -1,
|
|
[DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
|
|
[DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
|
|
[DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
|
|
[DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
|
|
[DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
|
|
[DEC_IRQ_AB_RXERR] = -1,
|
|
[DEC_IRQ_AB_RXDMA] = -1,
|
|
[DEC_IRQ_AB_TXERR] = -1,
|
|
[DEC_IRQ_AB_TXDMA] = -1,
|
|
[DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
|
|
[DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
|
|
[DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
|
|
[DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
|
|
};
|
|
|
|
static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
|
|
{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
|
|
{ .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
|
|
{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
|
|
{ .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
|
|
{ { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
|
|
{ .p = kn03_io_int } },
|
|
{ { .i = DEC_CPU_IRQ_ALL },
|
|
{ .p = cpu_all_int } },
|
|
};
|
|
|
|
static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
|
|
{ { .i = IO_IRQ_DMA },
|
|
{ .p = asic_dma_int } },
|
|
{ { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
|
|
{ .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
|
|
{ { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
|
|
{ .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
|
|
{ { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
|
|
{ .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
|
|
{ { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
|
|
{ .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
|
|
{ { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
|
|
{ .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
|
|
{ { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
|
|
{ .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
|
|
{ { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
|
|
{ .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
|
|
{ { .i = IO_IRQ_ALL },
|
|
{ .p = asic_all_int } },
|
|
};
|
|
|
|
static void __init dec_init_kn03(void)
|
|
{
|
|
/* IRQ routing. */
|
|
memcpy(&dec_interrupt, &kn03_interrupt,
|
|
sizeof(kn03_interrupt));
|
|
|
|
/* CPU IRQ priorities. */
|
|
memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
|
|
sizeof(kn03_cpu_mask_nr_tbl));
|
|
|
|
/* I/O ASIC IRQ priorities. */
|
|
memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
|
|
sizeof(kn03_asic_mask_nr_tbl));
|
|
|
|
mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
|
|
init_ioasic_irqs(IO_IRQ_BASE);
|
|
|
|
} /* dec_init_kn03 */
|
|
|
|
|
|
void __init arch_init_irq(void)
|
|
{
|
|
switch (mips_machtype) {
|
|
case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
|
|
dec_init_kn01();
|
|
break;
|
|
case MACH_DS5100: /* DS5100 MIPSmate */
|
|
dec_init_kn230();
|
|
break;
|
|
case MACH_DS5000_200: /* DS5000/200 3max */
|
|
dec_init_kn02();
|
|
break;
|
|
case MACH_DS5000_1XX: /* DS5000/1xx 3min */
|
|
dec_init_kn02ba();
|
|
break;
|
|
case MACH_DS5000_2X0: /* DS5000/240 3max+ */
|
|
case MACH_DS5900: /* DS5900 bigmax */
|
|
dec_init_kn03();
|
|
break;
|
|
case MACH_DS5000_XX: /* Personal DS5000/xx */
|
|
dec_init_kn02ca();
|
|
break;
|
|
case MACH_DS5800: /* DS5800 Isis */
|
|
panic("Don't know how to set this up!");
|
|
break;
|
|
case MACH_DS5400: /* DS5400 MIPSfair */
|
|
panic("Don't know how to set this up!");
|
|
break;
|
|
case MACH_DS5500: /* DS5500 MIPSfair-2 */
|
|
panic("Don't know how to set this up!");
|
|
break;
|
|
}
|
|
|
|
/* Free the FPU interrupt if the exception is present. */
|
|
if (!cpu_has_nofpuex) {
|
|
cpu_fpu_mask = 0;
|
|
dec_interrupt[DEC_IRQ_FPU] = -1;
|
|
}
|
|
|
|
/* Register board interrupts: FPU and cascade. */
|
|
if (dec_interrupt[DEC_IRQ_FPU] >= 0)
|
|
setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
|
|
if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
|
|
setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
|
|
|
|
/* Register the bus error interrupt. */
|
|
if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
|
|
setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
|
|
|
|
/* Register the HALT interrupt. */
|
|
if (dec_interrupt[DEC_IRQ_HALT] >= 0)
|
|
setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
|
|
}
|