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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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dfab34aa61
Device-tree updates for 3.10. The bulk of the churn in this branch is due to i.MX moving from C-defined pin control over to device tree, which is a one-time conversion that will allow greater flexibility down the road. Besides that, there's PCI-e bindings for Marvell mvebu platforms and a handful of cleanups to tegra due to the new include file functionality of the device tree compiler. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRgg+aAAoJEIwa5zzehBx3/q0P/RumfsMePxhmSU4HM16a3w0B 9jg7wd9BxVrJUzTY9F7z+Q72x0u5USUtVnyoY5s68DQMkFyhBQUuKCCiwCqtpCBN 2Uf0JQjYHdqEFKgN6DiPxSVRPXC8jmMzYGRk5RTI5kVWxaBEMdw9rTo0x4vol/Cv 7Z+W+gixXZbgydH/ogqly1MQc9vWliRTfU2zv2WOZ7TLyyEd2lOjMMBIX/n3vI4l T32JOUDgIYK841s9n2eNQGEjqB/OghMMrQsdjUAd++je6QtqgZk9+uHfPFC1C0wQ 3F93te9HleluYcOcxGmedK3B9QO2Y8y1XHe+uxLZVKXBR+6/5AtSwZFRQm10uMCI JUz3j6tRAWDAOin2vXZcf2CVPn5HZbh3D67WuUdfxMngH0XHvSZRC9eRd70jWvDe 9FY4NRTjRSLu/VtgCzF8tSA3cEylhyKYdK6Cf0nbwQ26JTO2VNNCnjuCbRfWp+E1 y0jIQwsaiNLEBwbesNbnFrj+YTTAZBI4+Y5HrSV7Og5/5X9BWs11KAkRppNOj0Uc WnqG26SssuBNBVHPOO2RrOwq3n2VphQ/BB8j9yrpWtcAlQxdjmVqFj/GIIiHr2Wm GuKWgM5fn+xF0oeCriq4Ti5eCJQ7Ev6Er46WrGQDBniZWVi05aP51ks1bfwbfHqn z1o5QfLpr4PkJPk0mnim =8X1b -----END PGP SIGNATURE----- Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device-tree updates from Olof Johansson: "Part 1 of device-tree updates for 3.10. The bulk of the churn in this branch is due to i.MX moving from C-defined pin control over to device tree, which is a one-time conversion that will allow greater flexibility down the road. Besides that, there's PCI-e bindings for Marvell mvebu platforms and a handful of cleanups to tegra due to the new include file functionality of the device tree compiler" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (113 commits) arm: mvebu: PCIe Device Tree informations for Armada XP GP arm: mvebu: PCIe Device Tree informations for Armada 370 DB arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox arm: mvebu: PCIe Device Tree informations for Armada XP DB arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 arm: mvebu: add PCIe Device Tree informations for Armada XP arm: mvebu: add PCIe Device Tree informations for Armada 370 ARM: sunxi: unify osc24M_fixed and osc24M arm: vt8500: Add SDHC support to WM8505 DT ARM: dts: Add a 64 bits version of the skeleton device tree ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board ARM: mvebu: Add support for NOR flash device on Armada XP-GP board ARM: mvebu: Add Device Bus support for Armada 370/XP SoC ARM: dts: imx6dl-wandboard: Add USB Host support ARM: dts: imx51 cpu node ARM: dts: Add missing imx27-phytec-phycore dtb target ARM: dts: Add NFC support for i.MX27 Phytec PCM038 module ARM: i.MX51: Add PATA support ARM: dts: Add initial support for Wandboard Dual-Lite ...
136 lines
2.7 KiB
Text
136 lines
2.7 KiB
Text
/*
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* Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Marvell Orion5x SoC";
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compatible = "marvell,orion5x";
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interrupt-parent = <&intc>;
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aliases {
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gpio0 = &gpio0;
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};
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intc: interrupt-controller {
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compatible = "marvell,orion-intc", "marvell,intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xf1020204 0x04>;
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};
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ocp@f1000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0xf1000000 0x4000000
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0xf2200000 0xf2200000 0x0000800>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpio0: gpio@10100 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0x10100 0x40>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <6>, <7>, <8>, <9>;
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};
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serial@12000 {
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compatible = "ns16550a";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <3>;
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/* set clock-frequency in board dts */
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status = "disabled";
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};
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serial@12100 {
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compatible = "ns16550a";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <4>;
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/* set clock-frequency in board dts */
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status = "disabled";
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};
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spi@10600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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reg = <0x10600 0x28>;
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status = "disabled";
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};
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wdt@20300 {
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compatible = "marvell,orion-wdt";
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reg = <0x20300 0x28>;
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status = "okay";
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};
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ehci@50000 {
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compatible = "marvell,orion-ehci";
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reg = <0x50000 0x1000>;
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interrupts = <17>;
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status = "disabled";
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};
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ehci@a0000 {
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compatible = "marvell,orion-ehci";
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reg = <0xa0000 0x1000>;
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interrupts = <12>;
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status = "disabled";
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};
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sata@80000 {
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compatible = "marvell,orion-sata";
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reg = <0x80000 0x5000>;
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interrupts = <29>;
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status = "disabled";
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};
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i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <5>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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xor@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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status = "okay";
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xor00 {
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interrupts = <30>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <31>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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crypto@90000 {
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compatible = "marvell,orion-crypto";
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reg = <0x90000 0x10000>,
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<0xf2200000 0x800>;
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reg-names = "regs", "sram";
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interrupts = <28>;
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status = "okay";
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};
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};
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};
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