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c62af12c70
On RZ/G2{L,LC} SoM module, the wm8978 audio codec is connected to ssi0,
whereas on RZ/G2UL it is connected to ssi1. So move ssi0 and cpu
sound_dai nodes from common dtsi to board specific dtsi.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220429072400.23729-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
65 lines
1.3 KiB
Text
65 lines
1.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
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#define PMOD1_SER0 1
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/ {
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aliases {
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serial1 = &scif2;
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i2c3 = &i2c3;
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};
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};
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&cpu_dai {
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sound-dai = <&ssi0>;
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};
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&i2c3 {
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pinctrl-0 = <&i2c3_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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wm8978: codec@1a {
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compatible = "wlf,wm8978";
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#sound-dai-cells = <0>;
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reg = <0x1a>;
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};
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};
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/*
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* To enable SCIF2 (SER0) on PMOD1 (CN7)
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* SW1 should be at position 2->3 so that SER0_CTS# line is activated
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* SW2 should be at position 2->3 so that SER0_TX line is activated
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* SW3 should be at position 2->3 so that SER0_RX line is activated
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* SW4 should be at position 2->3 so that SER0_RTS# line is activated
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*/
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#if PMOD1_SER0
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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#endif
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&ssi0 {
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pinctrl-0 = <&ssi0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&vccq_sdhi1 {
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gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
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};
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