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![Manivannan Sadhasivam](/assets/img/avatar_default.png)
Add support for managing the Memory Mapped Input Output (MMIO) registers of the MHI bus. All MHI operations are carried out using the MMIO registers by both host and the endpoint device. The MMIO registers reside inside the endpoint device memory (fixed location based on the platform) and the address is passed by the MHI EP controller driver during its registration. Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220405135754.6622-5-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
273 lines
6.9 KiB
C
273 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <linux/bitfield.h>
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#include <linux/io.h>
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#include <linux/mhi_ep.h>
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#include "internal.h"
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u32 mhi_ep_mmio_read(struct mhi_ep_cntrl *mhi_cntrl, u32 offset)
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{
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return readl(mhi_cntrl->mmio + offset);
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}
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void mhi_ep_mmio_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 val)
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{
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writel(val, mhi_cntrl->mmio + offset);
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}
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void mhi_ep_mmio_masked_write(struct mhi_ep_cntrl *mhi_cntrl, u32 offset, u32 mask, u32 val)
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{
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u32 regval;
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regval = mhi_ep_mmio_read(mhi_cntrl, offset);
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regval &= ~mask;
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regval |= (val << __ffs(mask)) & mask;
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mhi_ep_mmio_write(mhi_cntrl, offset, regval);
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}
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u32 mhi_ep_mmio_masked_read(struct mhi_ep_cntrl *dev, u32 offset, u32 mask)
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{
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u32 regval;
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regval = mhi_ep_mmio_read(dev, offset);
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regval &= mask;
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regval >>= __ffs(mask);
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return regval;
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}
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void mhi_ep_mmio_get_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state *state,
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bool *mhi_reset)
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{
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u32 regval;
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regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICTRL);
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*state = FIELD_GET(MHICTRL_MHISTATE_MASK, regval);
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*mhi_reset = !!FIELD_GET(MHICTRL_RESET_MASK, regval);
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}
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static void mhi_ep_mmio_set_chdb(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id, bool enable)
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{
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u32 chid_mask, chid_shift, chdb_idx, val;
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chid_shift = ch_id % 32;
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chid_mask = BIT(chid_shift);
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chdb_idx = ch_id / 32;
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val = enable ? 1 : 0;
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mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CHDB_INT_MASK_n(chdb_idx), chid_mask, val);
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/* Update the local copy of the channel mask */
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mhi_cntrl->chdb[chdb_idx].mask &= ~chid_mask;
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mhi_cntrl->chdb[chdb_idx].mask |= val << chid_shift;
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}
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void mhi_ep_mmio_enable_chdb(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id)
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{
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mhi_ep_mmio_set_chdb(mhi_cntrl, ch_id, true);
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}
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void mhi_ep_mmio_disable_chdb(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id)
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{
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mhi_ep_mmio_set_chdb(mhi_cntrl, ch_id, false);
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}
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static void mhi_ep_mmio_set_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl, bool enable)
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{
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u32 val, i;
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val = enable ? MHI_CHDB_INT_MASK_n_EN_ALL : 0;
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for (i = 0; i < MHI_MASK_ROWS_CH_DB; i++) {
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mhi_ep_mmio_write(mhi_cntrl, MHI_CHDB_INT_MASK_n(i), val);
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mhi_cntrl->chdb[i].mask = val;
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}
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}
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void mhi_ep_mmio_enable_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
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{
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mhi_ep_mmio_set_chdb_interrupts(mhi_cntrl, true);
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}
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static void mhi_ep_mmio_mask_chdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
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{
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mhi_ep_mmio_set_chdb_interrupts(mhi_cntrl, false);
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}
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bool mhi_ep_mmio_read_chdb_status_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
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{
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bool chdb = false;
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u32 i;
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for (i = 0; i < MHI_MASK_ROWS_CH_DB; i++) {
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mhi_cntrl->chdb[i].status = mhi_ep_mmio_read(mhi_cntrl, MHI_CHDB_INT_STATUS_n(i));
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if (mhi_cntrl->chdb[i].status)
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chdb = true;
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}
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/* Return whether a channel doorbell interrupt occurred or not */
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return chdb;
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}
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static void mhi_ep_mmio_set_erdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl, bool enable)
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{
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u32 val, i;
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val = enable ? MHI_ERDB_INT_MASK_n_EN_ALL : 0;
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for (i = 0; i < MHI_MASK_ROWS_EV_DB; i++)
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mhi_ep_mmio_write(mhi_cntrl, MHI_ERDB_INT_MASK_n(i), val);
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}
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static void mhi_ep_mmio_mask_erdb_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
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{
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mhi_ep_mmio_set_erdb_interrupts(mhi_cntrl, false);
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}
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void mhi_ep_mmio_enable_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl)
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{
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mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK,
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MHI_CTRL_MHICTRL_MASK, 1);
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}
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void mhi_ep_mmio_disable_ctrl_interrupt(struct mhi_ep_cntrl *mhi_cntrl)
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{
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mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK,
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MHI_CTRL_MHICTRL_MASK, 0);
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}
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void mhi_ep_mmio_enable_cmdb_interrupt(struct mhi_ep_cntrl *mhi_cntrl)
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{
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mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK,
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MHI_CTRL_CRDB_MASK, 1);
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}
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void mhi_ep_mmio_disable_cmdb_interrupt(struct mhi_ep_cntrl *mhi_cntrl)
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{
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mhi_ep_mmio_masked_write(mhi_cntrl, MHI_CTRL_INT_MASK,
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MHI_CTRL_CRDB_MASK, 0);
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}
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void mhi_ep_mmio_mask_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
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{
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mhi_ep_mmio_disable_ctrl_interrupt(mhi_cntrl);
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mhi_ep_mmio_disable_cmdb_interrupt(mhi_cntrl);
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mhi_ep_mmio_mask_chdb_interrupts(mhi_cntrl);
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mhi_ep_mmio_mask_erdb_interrupts(mhi_cntrl);
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}
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static void mhi_ep_mmio_clear_interrupts(struct mhi_ep_cntrl *mhi_cntrl)
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{
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u32 i;
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for (i = 0; i < MHI_MASK_ROWS_CH_DB; i++)
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mhi_ep_mmio_write(mhi_cntrl, MHI_CHDB_INT_CLEAR_n(i),
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MHI_CHDB_INT_CLEAR_n_CLEAR_ALL);
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for (i = 0; i < MHI_MASK_ROWS_EV_DB; i++)
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mhi_ep_mmio_write(mhi_cntrl, MHI_ERDB_INT_CLEAR_n(i),
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MHI_ERDB_INT_CLEAR_n_CLEAR_ALL);
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mhi_ep_mmio_write(mhi_cntrl, MHI_CTRL_INT_CLEAR,
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MHI_CTRL_INT_MMIO_WR_CLEAR |
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MHI_CTRL_INT_CRDB_CLEAR |
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MHI_CTRL_INT_CRDB_MHICTRL_CLEAR);
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}
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void mhi_ep_mmio_get_chc_base(struct mhi_ep_cntrl *mhi_cntrl)
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{
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u32 regval;
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regval = mhi_ep_mmio_read(mhi_cntrl, EP_CCABAP_HIGHER);
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mhi_cntrl->ch_ctx_host_pa = regval;
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mhi_cntrl->ch_ctx_host_pa <<= 32;
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regval = mhi_ep_mmio_read(mhi_cntrl, EP_CCABAP_LOWER);
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mhi_cntrl->ch_ctx_host_pa |= regval;
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}
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void mhi_ep_mmio_get_erc_base(struct mhi_ep_cntrl *mhi_cntrl)
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{
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u32 regval;
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regval = mhi_ep_mmio_read(mhi_cntrl, EP_ECABAP_HIGHER);
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mhi_cntrl->ev_ctx_host_pa = regval;
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mhi_cntrl->ev_ctx_host_pa <<= 32;
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regval = mhi_ep_mmio_read(mhi_cntrl, EP_ECABAP_LOWER);
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mhi_cntrl->ev_ctx_host_pa |= regval;
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}
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void mhi_ep_mmio_get_crc_base(struct mhi_ep_cntrl *mhi_cntrl)
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{
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u32 regval;
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regval = mhi_ep_mmio_read(mhi_cntrl, EP_CRCBAP_HIGHER);
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mhi_cntrl->cmd_ctx_host_pa = regval;
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mhi_cntrl->cmd_ctx_host_pa <<= 32;
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regval = mhi_ep_mmio_read(mhi_cntrl, EP_CRCBAP_LOWER);
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mhi_cntrl->cmd_ctx_host_pa |= regval;
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}
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u64 mhi_ep_mmio_get_db(struct mhi_ep_ring *ring)
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{
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struct mhi_ep_cntrl *mhi_cntrl = ring->mhi_cntrl;
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u64 db_offset;
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u32 regval;
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regval = mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_h);
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db_offset = regval;
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db_offset <<= 32;
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regval = mhi_ep_mmio_read(mhi_cntrl, ring->db_offset_l);
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db_offset |= regval;
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return db_offset;
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}
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void mhi_ep_mmio_set_env(struct mhi_ep_cntrl *mhi_cntrl, u32 value)
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{
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mhi_ep_mmio_write(mhi_cntrl, EP_BHI_EXECENV, value);
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}
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void mhi_ep_mmio_clear_reset(struct mhi_ep_cntrl *mhi_cntrl)
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{
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mhi_ep_mmio_masked_write(mhi_cntrl, EP_MHICTRL, MHICTRL_RESET_MASK, 0);
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}
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void mhi_ep_mmio_reset(struct mhi_ep_cntrl *mhi_cntrl)
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{
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mhi_ep_mmio_write(mhi_cntrl, EP_MHICTRL, 0);
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mhi_ep_mmio_write(mhi_cntrl, EP_MHISTATUS, 0);
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mhi_ep_mmio_clear_interrupts(mhi_cntrl);
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}
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void mhi_ep_mmio_init(struct mhi_ep_cntrl *mhi_cntrl)
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{
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u32 regval;
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mhi_cntrl->chdb_offset = mhi_ep_mmio_read(mhi_cntrl, EP_CHDBOFF);
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mhi_cntrl->erdb_offset = mhi_ep_mmio_read(mhi_cntrl, EP_ERDBOFF);
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regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICFG);
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mhi_cntrl->event_rings = FIELD_GET(MHICFG_NER_MASK, regval);
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mhi_cntrl->hw_event_rings = FIELD_GET(MHICFG_NHWER_MASK, regval);
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mhi_ep_mmio_reset(mhi_cntrl);
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}
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void mhi_ep_mmio_update_ner(struct mhi_ep_cntrl *mhi_cntrl)
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{
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u32 regval;
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regval = mhi_ep_mmio_read(mhi_cntrl, EP_MHICFG);
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mhi_cntrl->event_rings = FIELD_GET(MHICFG_NER_MASK, regval);
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mhi_cntrl->hw_event_rings = FIELD_GET(MHICFG_NHWER_MASK, regval);
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}
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