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![Pavel Pisa](/assets/img/avatar_default.png)
The update is compatible/pure extension of 2.x IP core version - new option for 2, 4, or 8 Tx buffers option during synthesis. The 2.x version has fixed 4 Tx buffers. 3.x version default is 4 as well - new REG_TX_COMMAND_TXT_BUFFER_COUNT provides synthesis choice. When read as 0 assume 2.x core with fixed 4 Tx buffers. - new REG_ERR_CAPT_TS_BITS field to provide most significant active/implemented timestamp bit. For 2.x read as zero, assume value 63 is such case for 64 bit counter. - new REG_MODE_RXBAM bit which controls automatic advance to next word after Rx FIFO register read. Bit is set to 1 by default after the core reset (REG_MODE_RST) and value 1 has to be preserved for the normal ctucanfd Linux driver operation. Even preceding driver version resets core and then modifies only known/required MODE register bits so backward and forward compatibility is ensured. See complete datasheet for time-triggered and other updated capabilities http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf The fields related to ongoing Ondrej Ille's work on fault tolerant version with parity protected buffers and FIFOs are not included for now. Their inclusion will be considered when design is settled and tested. Link: https://lore.kernel.org/all/14a98ed1829121f0f3bde784f1aa533bc3cc7fe0.1658139843.git.pisa@cmp.felk.cvut.cz Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
349 lines
11 KiB
C
349 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*******************************************************************************
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*
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* CTU CAN FD IP Core
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*
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* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
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* Copyright (C) 2018-2022 Ondrej Ille <ondrej.ille@gmail.com> self-funded
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* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
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* Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
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*
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* Project advisors:
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* Jiri Novak <jnovak@fel.cvut.cz>
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* Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Department of Measurement (http://meas.fel.cvut.cz/)
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* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
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* Czech Technical University (http://www.cvut.cz/)
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******************************************************************************/
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/* This file is autogenerated, DO NOT EDIT! */
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#ifndef __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
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#define __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
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#include <linux/bits.h>
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/* CAN_Registers memory map */
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enum ctu_can_fd_can_registers {
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CTUCANFD_DEVICE_ID = 0x0,
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CTUCANFD_VERSION = 0x2,
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CTUCANFD_MODE = 0x4,
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CTUCANFD_SETTINGS = 0x6,
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CTUCANFD_STATUS = 0x8,
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CTUCANFD_COMMAND = 0xc,
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CTUCANFD_INT_STAT = 0x10,
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CTUCANFD_INT_ENA_SET = 0x14,
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CTUCANFD_INT_ENA_CLR = 0x18,
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CTUCANFD_INT_MASK_SET = 0x1c,
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CTUCANFD_INT_MASK_CLR = 0x20,
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CTUCANFD_BTR = 0x24,
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CTUCANFD_BTR_FD = 0x28,
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CTUCANFD_EWL = 0x2c,
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CTUCANFD_ERP = 0x2d,
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CTUCANFD_FAULT_STATE = 0x2e,
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CTUCANFD_REC = 0x30,
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CTUCANFD_TEC = 0x32,
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CTUCANFD_ERR_NORM = 0x34,
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CTUCANFD_ERR_FD = 0x36,
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CTUCANFD_CTR_PRES = 0x38,
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CTUCANFD_FILTER_A_MASK = 0x3c,
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CTUCANFD_FILTER_A_VAL = 0x40,
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CTUCANFD_FILTER_B_MASK = 0x44,
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CTUCANFD_FILTER_B_VAL = 0x48,
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CTUCANFD_FILTER_C_MASK = 0x4c,
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CTUCANFD_FILTER_C_VAL = 0x50,
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CTUCANFD_FILTER_RAN_LOW = 0x54,
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CTUCANFD_FILTER_RAN_HIGH = 0x58,
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CTUCANFD_FILTER_CONTROL = 0x5c,
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CTUCANFD_FILTER_STATUS = 0x5e,
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CTUCANFD_RX_MEM_INFO = 0x60,
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CTUCANFD_RX_POINTERS = 0x64,
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CTUCANFD_RX_STATUS = 0x68,
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CTUCANFD_RX_SETTINGS = 0x6a,
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CTUCANFD_RX_DATA = 0x6c,
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CTUCANFD_TX_STATUS = 0x70,
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CTUCANFD_TX_COMMAND = 0x74,
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CTUCANFD_TXTB_INFO = 0x76,
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CTUCANFD_TX_PRIORITY = 0x78,
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CTUCANFD_ERR_CAPT = 0x7c,
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CTUCANFD_RETR_CTR = 0x7d,
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CTUCANFD_ALC = 0x7e,
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CTUCANFD_TS_INFO = 0x7f,
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CTUCANFD_TRV_DELAY = 0x80,
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CTUCANFD_SSP_CFG = 0x82,
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CTUCANFD_RX_FR_CTR = 0x84,
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CTUCANFD_TX_FR_CTR = 0x88,
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CTUCANFD_DEBUG_REGISTER = 0x8c,
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CTUCANFD_YOLO_REG = 0x90,
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CTUCANFD_TIMESTAMP_LOW = 0x94,
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CTUCANFD_TIMESTAMP_HIGH = 0x98,
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CTUCANFD_TXTB1_DATA_1 = 0x100,
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CTUCANFD_TXTB1_DATA_2 = 0x104,
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CTUCANFD_TXTB1_DATA_20 = 0x14c,
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CTUCANFD_TXTB2_DATA_1 = 0x200,
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CTUCANFD_TXTB2_DATA_2 = 0x204,
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CTUCANFD_TXTB2_DATA_20 = 0x24c,
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CTUCANFD_TXTB3_DATA_1 = 0x300,
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CTUCANFD_TXTB3_DATA_2 = 0x304,
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CTUCANFD_TXTB3_DATA_20 = 0x34c,
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CTUCANFD_TXTB4_DATA_1 = 0x400,
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CTUCANFD_TXTB4_DATA_2 = 0x404,
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CTUCANFD_TXTB4_DATA_20 = 0x44c,
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};
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/* Control_registers memory region */
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/* DEVICE_ID VERSION registers */
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#define REG_DEVICE_ID_DEVICE_ID GENMASK(15, 0)
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#define REG_DEVICE_ID_VER_MINOR GENMASK(23, 16)
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#define REG_DEVICE_ID_VER_MAJOR GENMASK(31, 24)
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/* MODE SETTINGS registers */
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#define REG_MODE_RST BIT(0)
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#define REG_MODE_BMM BIT(1)
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#define REG_MODE_STM BIT(2)
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#define REG_MODE_AFM BIT(3)
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#define REG_MODE_FDE BIT(4)
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#define REG_MODE_TTTM BIT(5)
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#define REG_MODE_ROM BIT(6)
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#define REG_MODE_ACF BIT(7)
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#define REG_MODE_TSTM BIT(8)
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#define REG_MODE_RXBAM BIT(9)
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#define REG_MODE_SAM BIT(11)
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#define REG_MODE_RTRLE BIT(16)
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#define REG_MODE_RTRTH GENMASK(20, 17)
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#define REG_MODE_ILBP BIT(21)
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#define REG_MODE_ENA BIT(22)
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#define REG_MODE_NISOFD BIT(23)
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#define REG_MODE_PEX BIT(24)
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#define REG_MODE_TBFBO BIT(25)
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#define REG_MODE_FDRF BIT(26)
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/* STATUS registers */
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#define REG_STATUS_RXNE BIT(0)
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#define REG_STATUS_DOR BIT(1)
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#define REG_STATUS_TXNF BIT(2)
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#define REG_STATUS_EFT BIT(3)
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#define REG_STATUS_RXS BIT(4)
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#define REG_STATUS_TXS BIT(5)
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#define REG_STATUS_EWL BIT(6)
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#define REG_STATUS_IDLE BIT(7)
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#define REG_STATUS_PEXS BIT(8)
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#define REG_STATUS_STCNT BIT(16)
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/* COMMAND registers */
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#define REG_COMMAND_RXRPMV BIT(1)
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#define REG_COMMAND_RRB BIT(2)
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#define REG_COMMAND_CDO BIT(3)
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#define REG_COMMAND_ERCRST BIT(4)
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#define REG_COMMAND_RXFCRST BIT(5)
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#define REG_COMMAND_TXFCRST BIT(6)
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#define REG_COMMAND_CPEXS BIT(7)
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/* INT_STAT registers */
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#define REG_INT_STAT_RXI BIT(0)
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#define REG_INT_STAT_TXI BIT(1)
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#define REG_INT_STAT_EWLI BIT(2)
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#define REG_INT_STAT_DOI BIT(3)
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#define REG_INT_STAT_FCSI BIT(4)
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#define REG_INT_STAT_ALI BIT(5)
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#define REG_INT_STAT_BEI BIT(6)
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#define REG_INT_STAT_OFI BIT(7)
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#define REG_INT_STAT_RXFI BIT(8)
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#define REG_INT_STAT_BSI BIT(9)
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#define REG_INT_STAT_RBNEI BIT(10)
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#define REG_INT_STAT_TXBHCI BIT(11)
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/* INT_ENA_SET registers */
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#define REG_INT_ENA_SET_INT_ENA_SET GENMASK(11, 0)
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/* INT_ENA_CLR registers */
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#define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK(11, 0)
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/* INT_MASK_SET registers */
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#define REG_INT_MASK_SET_INT_MASK_SET GENMASK(11, 0)
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/* INT_MASK_CLR registers */
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#define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK(11, 0)
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/* BTR registers */
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#define REG_BTR_PROP GENMASK(6, 0)
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#define REG_BTR_PH1 GENMASK(12, 7)
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#define REG_BTR_PH2 GENMASK(18, 13)
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#define REG_BTR_BRP GENMASK(26, 19)
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#define REG_BTR_SJW GENMASK(31, 27)
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/* BTR_FD registers */
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#define REG_BTR_FD_PROP_FD GENMASK(5, 0)
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#define REG_BTR_FD_PH1_FD GENMASK(11, 7)
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#define REG_BTR_FD_PH2_FD GENMASK(17, 13)
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#define REG_BTR_FD_BRP_FD GENMASK(26, 19)
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#define REG_BTR_FD_SJW_FD GENMASK(31, 27)
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/* EWL ERP FAULT_STATE registers */
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#define REG_EWL_EW_LIMIT GENMASK(7, 0)
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#define REG_EWL_ERP_LIMIT GENMASK(15, 8)
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#define REG_EWL_ERA BIT(16)
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#define REG_EWL_ERP BIT(17)
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#define REG_EWL_BOF BIT(18)
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/* REC TEC registers */
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#define REG_REC_REC_VAL GENMASK(8, 0)
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#define REG_REC_TEC_VAL GENMASK(24, 16)
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/* ERR_NORM ERR_FD registers */
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#define REG_ERR_NORM_ERR_NORM_VAL GENMASK(15, 0)
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#define REG_ERR_NORM_ERR_FD_VAL GENMASK(31, 16)
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/* CTR_PRES registers */
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#define REG_CTR_PRES_CTPV GENMASK(8, 0)
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#define REG_CTR_PRES_PTX BIT(9)
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#define REG_CTR_PRES_PRX BIT(10)
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#define REG_CTR_PRES_ENORM BIT(11)
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#define REG_CTR_PRES_EFD BIT(12)
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/* FILTER_A_MASK registers */
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#define REG_FILTER_A_MASK_BIT_MASK_A_VAL GENMASK(28, 0)
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/* FILTER_A_VAL registers */
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#define REG_FILTER_A_VAL_BIT_VAL_A_VAL GENMASK(28, 0)
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/* FILTER_B_MASK registers */
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#define REG_FILTER_B_MASK_BIT_MASK_B_VAL GENMASK(28, 0)
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/* FILTER_B_VAL registers */
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#define REG_FILTER_B_VAL_BIT_VAL_B_VAL GENMASK(28, 0)
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/* FILTER_C_MASK registers */
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#define REG_FILTER_C_MASK_BIT_MASK_C_VAL GENMASK(28, 0)
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/* FILTER_C_VAL registers */
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#define REG_FILTER_C_VAL_BIT_VAL_C_VAL GENMASK(28, 0)
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/* FILTER_RAN_LOW registers */
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#define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL GENMASK(28, 0)
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/* FILTER_RAN_HIGH registers */
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#define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL GENMASK(28, 0)
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/* FILTER_CONTROL FILTER_STATUS registers */
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#define REG_FILTER_CONTROL_FANB BIT(0)
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#define REG_FILTER_CONTROL_FANE BIT(1)
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#define REG_FILTER_CONTROL_FAFB BIT(2)
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#define REG_FILTER_CONTROL_FAFE BIT(3)
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#define REG_FILTER_CONTROL_FBNB BIT(4)
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#define REG_FILTER_CONTROL_FBNE BIT(5)
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#define REG_FILTER_CONTROL_FBFB BIT(6)
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#define REG_FILTER_CONTROL_FBFE BIT(7)
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#define REG_FILTER_CONTROL_FCNB BIT(8)
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#define REG_FILTER_CONTROL_FCNE BIT(9)
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#define REG_FILTER_CONTROL_FCFB BIT(10)
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#define REG_FILTER_CONTROL_FCFE BIT(11)
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#define REG_FILTER_CONTROL_FRNB BIT(12)
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#define REG_FILTER_CONTROL_FRNE BIT(13)
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#define REG_FILTER_CONTROL_FRFB BIT(14)
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#define REG_FILTER_CONTROL_FRFE BIT(15)
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#define REG_FILTER_CONTROL_SFA BIT(16)
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#define REG_FILTER_CONTROL_SFB BIT(17)
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#define REG_FILTER_CONTROL_SFC BIT(18)
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#define REG_FILTER_CONTROL_SFR BIT(19)
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/* RX_MEM_INFO registers */
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#define REG_RX_MEM_INFO_RX_BUFF_SIZE GENMASK(12, 0)
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#define REG_RX_MEM_INFO_RX_MEM_FREE GENMASK(28, 16)
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/* RX_POINTERS registers */
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#define REG_RX_POINTERS_RX_WPP GENMASK(11, 0)
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#define REG_RX_POINTERS_RX_RPP GENMASK(27, 16)
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/* RX_STATUS RX_SETTINGS registers */
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#define REG_RX_STATUS_RXE BIT(0)
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#define REG_RX_STATUS_RXF BIT(1)
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#define REG_RX_STATUS_RXMOF BIT(2)
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#define REG_RX_STATUS_RXFRC GENMASK(14, 4)
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#define REG_RX_STATUS_RTSOP BIT(16)
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/* RX_DATA registers */
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#define REG_RX_DATA_RX_DATA GENMASK(31, 0)
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/* TX_STATUS registers */
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#define REG_TX_STATUS_TX1S GENMASK(3, 0)
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#define REG_TX_STATUS_TX2S GENMASK(7, 4)
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#define REG_TX_STATUS_TX3S GENMASK(11, 8)
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#define REG_TX_STATUS_TX4S GENMASK(15, 12)
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#define REG_TX_STATUS_TX5S GENMASK(19, 16)
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#define REG_TX_STATUS_TX6S GENMASK(23, 20)
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#define REG_TX_STATUS_TX7S GENMASK(27, 24)
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#define REG_TX_STATUS_TX8S GENMASK(31, 28)
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/* TX_COMMAND TXTB_INFO registers */
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#define REG_TX_COMMAND_TXCE BIT(0)
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#define REG_TX_COMMAND_TXCR BIT(1)
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#define REG_TX_COMMAND_TXCA BIT(2)
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#define REG_TX_COMMAND_TXB1 BIT(8)
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#define REG_TX_COMMAND_TXB2 BIT(9)
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#define REG_TX_COMMAND_TXB3 BIT(10)
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#define REG_TX_COMMAND_TXB4 BIT(11)
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#define REG_TX_COMMAND_TXB5 BIT(12)
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#define REG_TX_COMMAND_TXB6 BIT(13)
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#define REG_TX_COMMAND_TXB7 BIT(14)
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#define REG_TX_COMMAND_TXB8 BIT(15)
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#define REG_TX_COMMAND_TXT_BUFFER_COUNT GENMASK(19, 16)
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/* TX_PRIORITY registers */
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#define REG_TX_PRIORITY_TXT1P GENMASK(2, 0)
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#define REG_TX_PRIORITY_TXT2P GENMASK(6, 4)
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#define REG_TX_PRIORITY_TXT3P GENMASK(10, 8)
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#define REG_TX_PRIORITY_TXT4P GENMASK(14, 12)
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#define REG_TX_PRIORITY_TXT5P GENMASK(18, 16)
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#define REG_TX_PRIORITY_TXT6P GENMASK(22, 20)
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#define REG_TX_PRIORITY_TXT7P GENMASK(26, 24)
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#define REG_TX_PRIORITY_TXT8P GENMASK(30, 28)
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/* ERR_CAPT RETR_CTR ALC TS_INFO registers */
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#define REG_ERR_CAPT_ERR_POS GENMASK(4, 0)
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#define REG_ERR_CAPT_ERR_TYPE GENMASK(7, 5)
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#define REG_ERR_CAPT_RETR_CTR_VAL GENMASK(11, 8)
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#define REG_ERR_CAPT_ALC_BIT GENMASK(20, 16)
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#define REG_ERR_CAPT_ALC_ID_FIELD GENMASK(23, 21)
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#define REG_ERR_CAPT_TS_BITS GENMASK(29, 24)
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/* TRV_DELAY SSP_CFG registers */
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#define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK(6, 0)
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#define REG_TRV_DELAY_SSP_OFFSET GENMASK(23, 16)
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#define REG_TRV_DELAY_SSP_SRC GENMASK(25, 24)
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/* RX_FR_CTR registers */
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#define REG_RX_FR_CTR_RX_FR_CTR_VAL GENMASK(31, 0)
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/* TX_FR_CTR registers */
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#define REG_TX_FR_CTR_TX_FR_CTR_VAL GENMASK(31, 0)
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/* DEBUG_REGISTER registers */
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#define REG_DEBUG_REGISTER_STUFF_COUNT GENMASK(2, 0)
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#define REG_DEBUG_REGISTER_DESTUFF_COUNT GENMASK(5, 3)
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#define REG_DEBUG_REGISTER_PC_ARB BIT(6)
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#define REG_DEBUG_REGISTER_PC_CON BIT(7)
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#define REG_DEBUG_REGISTER_PC_DAT BIT(8)
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#define REG_DEBUG_REGISTER_PC_STC BIT(9)
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#define REG_DEBUG_REGISTER_PC_CRC BIT(10)
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#define REG_DEBUG_REGISTER_PC_CRCD BIT(11)
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#define REG_DEBUG_REGISTER_PC_ACK BIT(12)
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#define REG_DEBUG_REGISTER_PC_ACKD BIT(13)
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#define REG_DEBUG_REGISTER_PC_EOF BIT(14)
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#define REG_DEBUG_REGISTER_PC_INT BIT(15)
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#define REG_DEBUG_REGISTER_PC_SUSP BIT(16)
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#define REG_DEBUG_REGISTER_PC_OVR BIT(17)
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#define REG_DEBUG_REGISTER_PC_SOF BIT(18)
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/* YOLO_REG registers */
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#define REG_YOLO_REG_YOLO_VAL GENMASK(31, 0)
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/* TIMESTAMP_LOW registers */
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#define REG_TIMESTAMP_LOW_TIMESTAMP_LOW GENMASK(31, 0)
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/* TIMESTAMP_HIGH registers */
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#define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH GENMASK(31, 0)
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#endif
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