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c1b17ea7dd
To reduce debugging effort in case the mram is misconfigured, add this size check of the DT configuration. Currently if the mram configuration doesn't fit into the available MRAM it just overwrites other areas of the MRAM. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Reviewed-by: Michal Kubiak <michal.kubiak@intel.com> Link: https://lore.kernel.org/all/20230728141923.162477-4-msp@baylibre.com Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
110 lines
2.7 KiB
C
110 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* CAN bus driver for Bosch M_CAN controller
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef _CAN_M_CAN_H_
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#define _CAN_M_CAN_H_
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#include <linux/can/core.h>
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#include <linux/can/dev.h>
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#include <linux/can/rx-offload.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/freezer.h>
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#include <linux/hrtimer.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/of.h>
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#include <linux/phy/phy.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/uaccess.h>
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/* m_can lec values */
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enum m_can_lec_type {
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LEC_NO_ERROR = 0,
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LEC_STUFF_ERROR,
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LEC_FORM_ERROR,
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LEC_ACK_ERROR,
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LEC_BIT1_ERROR,
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LEC_BIT0_ERROR,
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LEC_CRC_ERROR,
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LEC_NO_CHANGE,
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};
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enum m_can_mram_cfg {
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MRAM_SIDF = 0,
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MRAM_XIDF,
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MRAM_RXF0,
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MRAM_RXF1,
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MRAM_RXB,
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MRAM_TXE,
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MRAM_TXB,
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MRAM_CFG_NUM,
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};
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/* address offset and element number for each FIFO/Buffer in the Message RAM */
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struct mram_cfg {
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u16 off;
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u8 num;
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};
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struct m_can_classdev;
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struct m_can_ops {
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/* Device specific call backs */
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int (*clear_interrupts)(struct m_can_classdev *cdev);
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u32 (*read_reg)(struct m_can_classdev *cdev, int reg);
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int (*write_reg)(struct m_can_classdev *cdev, int reg, int val);
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int (*read_fifo)(struct m_can_classdev *cdev, int addr_offset, void *val, size_t val_count);
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int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset,
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const void *val, size_t val_count);
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int (*init)(struct m_can_classdev *cdev);
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};
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struct m_can_classdev {
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struct can_priv can;
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struct can_rx_offload offload;
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struct napi_struct napi;
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struct net_device *net;
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struct device *dev;
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struct clk *hclk;
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struct clk *cclk;
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struct workqueue_struct *tx_wq;
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struct work_struct tx_work;
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struct sk_buff *tx_skb;
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struct phy *transceiver;
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struct m_can_ops *ops;
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int version;
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u32 irqstatus;
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int pm_clock_support;
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int is_peripheral;
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struct mram_cfg mcfg[MRAM_CFG_NUM];
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struct hrtimer hrtimer;
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};
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struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv);
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void m_can_class_free_dev(struct net_device *net);
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int m_can_class_register(struct m_can_classdev *cdev);
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void m_can_class_unregister(struct m_can_classdev *cdev);
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int m_can_class_get_clocks(struct m_can_classdev *cdev);
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int m_can_init_ram(struct m_can_classdev *priv);
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int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size);
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int m_can_class_suspend(struct device *dev);
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int m_can_class_resume(struct device *dev);
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#endif /* _CAN_M_H_ */
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