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On LPAR systems we need to inform the hypervisor that we are using the EBB registers. We do this by setting a bit in the Virtual Processor Area (VPA) - formerly known as the lppaca. For now we do this always, ie. we do not dynamically enable/disable. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
158 lines
4.7 KiB
C
158 lines
4.7 KiB
C
/*
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* lppaca.h
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* Copyright (C) 2001 Mike Corrigan IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_POWERPC_LPPACA_H
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#define _ASM_POWERPC_LPPACA_H
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#ifdef __KERNEL__
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/*
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* These definitions relate to hypervisors that only exist when using
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* a server type processor
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*/
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#ifdef CONFIG_PPC_BOOK3S
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/*
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* This control block contains the data that is shared between the
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* hypervisor and the OS.
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*/
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#include <linux/cache.h>
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#include <linux/threads.h>
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#include <asm/types.h>
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#include <asm/mmu.h>
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/*
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* We only have to have statically allocated lppaca structs on
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* legacy iSeries, which supports at most 64 cpus.
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*/
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#define NR_LPPACAS 1
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/*
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* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k
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* alignment is sufficient to prevent this
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*/
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struct lppaca {
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/* cacheline 1 contains read-only data */
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u32 desc; /* Eye catcher 0xD397D781 */
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u16 size; /* Size of this struct */
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u16 reserved1;
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u16 reserved2:14;
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u8 shared_proc:1; /* Shared processor indicator */
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u8 secondary_thread:1; /* Secondary thread indicator */
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u8 reserved3[14];
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volatile u32 dyn_hw_node_id; /* Dynamic hardware node id */
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volatile u32 dyn_hw_proc_id; /* Dynamic hardware proc id */
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u8 reserved4[56];
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volatile u8 vphn_assoc_counts[8]; /* Virtual processor home node */
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/* associativity change counters */
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u8 reserved5[32];
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/* cacheline 2 contains local read-write data */
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u8 reserved6[48];
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u8 cede_latency_hint;
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u8 ebb_regs_in_use;
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u8 reserved7[6];
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u8 dtl_enable_mask; /* Dispatch Trace Log mask */
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u8 donate_dedicated_cpu; /* Donate dedicated CPU cycles */
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u8 fpregs_in_use;
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u8 pmcregs_in_use;
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u8 reserved8[28];
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u64 wait_state_cycles; /* Wait cycles for this proc */
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u8 reserved9[28];
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u16 slb_count; /* # of SLBs to maintain */
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u8 idle; /* Indicate OS is idle */
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u8 vmxregs_in_use;
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/* cacheline 3 is shared with other processors */
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/*
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* This is the yield_count. An "odd" value (low bit on) means that
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* the processor is yielded (either because of an OS yield or a
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* hypervisor preempt). An even value implies that the processor is
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* currently executing.
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* NOTE: This value will ALWAYS be zero for dedicated processors and
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* will NEVER be zero for shared processors (ie, initialized to a 1).
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*/
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volatile u32 yield_count;
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volatile u32 dispersion_count; /* dispatch changed physical cpu */
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volatile u64 cmo_faults; /* CMO page fault count */
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volatile u64 cmo_fault_time; /* CMO page fault time */
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u8 reserved10[104];
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/* cacheline 4-5 */
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u32 page_ins; /* CMO Hint - # page ins by OS */
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u8 reserved11[148];
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volatile u64 dtl_idx; /* Dispatch Trace Log head index */
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u8 reserved12[96];
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} __attribute__((__aligned__(0x400)));
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extern struct lppaca lppaca[];
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#define lppaca_of(cpu) (*paca[cpu].lppaca_ptr)
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/*
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* SLB shadow buffer structure as defined in the PAPR. The save_area
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* contains adjacent ESID and VSID pairs for each shadowed SLB. The
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* ESID is stored in the lower 64bits, then the VSID.
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*/
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struct slb_shadow {
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u32 persistent; /* Number of persistent SLBs */
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u32 buffer_length; /* Total shadow buffer length */
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u64 reserved;
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struct {
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u64 esid;
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u64 vsid;
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} save_area[SLB_NUM_BOLTED];
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} ____cacheline_aligned;
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extern struct slb_shadow slb_shadow[];
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/*
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* Layout of entries in the hypervisor's dispatch trace log buffer.
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*/
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struct dtl_entry {
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u8 dispatch_reason;
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u8 preempt_reason;
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u16 processor_id;
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u32 enqueue_to_dispatch_time;
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u32 ready_to_enqueue_time;
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u32 waiting_to_ready_time;
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u64 timebase;
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u64 fault_addr;
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u64 srr0;
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u64 srr1;
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};
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#define DISPATCH_LOG_BYTES 4096 /* bytes per cpu */
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#define N_DISPATCH_LOG (DISPATCH_LOG_BYTES / sizeof(struct dtl_entry))
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extern struct kmem_cache *dtl_cache;
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/*
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* When CONFIG_VIRT_CPU_ACCOUNTING_NATIVE = y, the cpu accounting code controls
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* reading from the dispatch trace log. If other code wants to consume
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* DTL entries, it can set this pointer to a function that will get
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* called once for each DTL entry that gets processed.
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*/
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extern void (*dtl_consumer)(struct dtl_entry *entry, u64 index);
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#endif /* CONFIG_PPC_BOOK3S */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_LPPACA_H */
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