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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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886 lines
22 KiB
C
886 lines
22 KiB
C
/*
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* IPMMU VMSA
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <asm/dma-iommu.h>
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#include <asm/pgalloc.h>
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#include "io-pgtable.h"
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struct ipmmu_vmsa_device {
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struct device *dev;
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void __iomem *base;
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struct list_head list;
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unsigned int num_utlbs;
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struct dma_iommu_mapping *mapping;
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};
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struct ipmmu_vmsa_domain {
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struct ipmmu_vmsa_device *mmu;
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struct iommu_domain io_domain;
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struct io_pgtable_cfg cfg;
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struct io_pgtable_ops *iop;
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unsigned int context_id;
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spinlock_t lock; /* Protects mappings */
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};
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struct ipmmu_vmsa_archdata {
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struct ipmmu_vmsa_device *mmu;
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unsigned int *utlbs;
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unsigned int num_utlbs;
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};
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static DEFINE_SPINLOCK(ipmmu_devices_lock);
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static LIST_HEAD(ipmmu_devices);
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static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
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{
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return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
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}
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#define TLB_LOOP_TIMEOUT 100 /* 100us */
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/* -----------------------------------------------------------------------------
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* Registers Definition
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*/
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#define IM_NS_ALIAS_OFFSET 0x800
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#define IM_CTX_SIZE 0x40
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#define IMCTR 0x0000
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#define IMCTR_TRE (1 << 17)
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#define IMCTR_AFE (1 << 16)
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#define IMCTR_RTSEL_MASK (3 << 4)
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#define IMCTR_RTSEL_SHIFT 4
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#define IMCTR_TREN (1 << 3)
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#define IMCTR_INTEN (1 << 2)
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#define IMCTR_FLUSH (1 << 1)
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#define IMCTR_MMUEN (1 << 0)
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#define IMCAAR 0x0004
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#define IMTTBCR 0x0008
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#define IMTTBCR_EAE (1 << 31)
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#define IMTTBCR_PMB (1 << 30)
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#define IMTTBCR_SH1_NON_SHAREABLE (0 << 28)
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#define IMTTBCR_SH1_OUTER_SHAREABLE (2 << 28)
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#define IMTTBCR_SH1_INNER_SHAREABLE (3 << 28)
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#define IMTTBCR_SH1_MASK (3 << 28)
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#define IMTTBCR_ORGN1_NC (0 << 26)
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#define IMTTBCR_ORGN1_WB_WA (1 << 26)
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#define IMTTBCR_ORGN1_WT (2 << 26)
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#define IMTTBCR_ORGN1_WB (3 << 26)
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#define IMTTBCR_ORGN1_MASK (3 << 26)
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#define IMTTBCR_IRGN1_NC (0 << 24)
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#define IMTTBCR_IRGN1_WB_WA (1 << 24)
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#define IMTTBCR_IRGN1_WT (2 << 24)
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#define IMTTBCR_IRGN1_WB (3 << 24)
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#define IMTTBCR_IRGN1_MASK (3 << 24)
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#define IMTTBCR_TSZ1_MASK (7 << 16)
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#define IMTTBCR_TSZ1_SHIFT 16
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#define IMTTBCR_SH0_NON_SHAREABLE (0 << 12)
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#define IMTTBCR_SH0_OUTER_SHAREABLE (2 << 12)
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#define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12)
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#define IMTTBCR_SH0_MASK (3 << 12)
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#define IMTTBCR_ORGN0_NC (0 << 10)
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#define IMTTBCR_ORGN0_WB_WA (1 << 10)
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#define IMTTBCR_ORGN0_WT (2 << 10)
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#define IMTTBCR_ORGN0_WB (3 << 10)
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#define IMTTBCR_ORGN0_MASK (3 << 10)
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#define IMTTBCR_IRGN0_NC (0 << 8)
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#define IMTTBCR_IRGN0_WB_WA (1 << 8)
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#define IMTTBCR_IRGN0_WT (2 << 8)
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#define IMTTBCR_IRGN0_WB (3 << 8)
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#define IMTTBCR_IRGN0_MASK (3 << 8)
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#define IMTTBCR_SL0_LVL_2 (0 << 4)
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#define IMTTBCR_SL0_LVL_1 (1 << 4)
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#define IMTTBCR_TSZ0_MASK (7 << 0)
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#define IMTTBCR_TSZ0_SHIFT O
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#define IMBUSCR 0x000c
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#define IMBUSCR_DVM (1 << 2)
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#define IMBUSCR_BUSSEL_SYS (0 << 0)
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#define IMBUSCR_BUSSEL_CCI (1 << 0)
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#define IMBUSCR_BUSSEL_IMCAAR (2 << 0)
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#define IMBUSCR_BUSSEL_CCI_IMCAAR (3 << 0)
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#define IMBUSCR_BUSSEL_MASK (3 << 0)
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#define IMTTLBR0 0x0010
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#define IMTTUBR0 0x0014
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#define IMTTLBR1 0x0018
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#define IMTTUBR1 0x001c
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#define IMSTR 0x0020
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#define IMSTR_ERRLVL_MASK (3 << 12)
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#define IMSTR_ERRLVL_SHIFT 12
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#define IMSTR_ERRCODE_TLB_FORMAT (1 << 8)
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#define IMSTR_ERRCODE_ACCESS_PERM (4 << 8)
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#define IMSTR_ERRCODE_SECURE_ACCESS (5 << 8)
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#define IMSTR_ERRCODE_MASK (7 << 8)
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#define IMSTR_MHIT (1 << 4)
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#define IMSTR_ABORT (1 << 2)
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#define IMSTR_PF (1 << 1)
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#define IMSTR_TF (1 << 0)
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#define IMMAIR0 0x0028
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#define IMMAIR1 0x002c
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#define IMMAIR_ATTR_MASK 0xff
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#define IMMAIR_ATTR_DEVICE 0x04
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#define IMMAIR_ATTR_NC 0x44
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#define IMMAIR_ATTR_WBRWA 0xff
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#define IMMAIR_ATTR_SHIFT(n) ((n) << 3)
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#define IMMAIR_ATTR_IDX_NC 0
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#define IMMAIR_ATTR_IDX_WBRWA 1
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#define IMMAIR_ATTR_IDX_DEV 2
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#define IMEAR 0x0030
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#define IMPCTR 0x0200
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#define IMPSTR 0x0208
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#define IMPEAR 0x020c
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#define IMPMBA(n) (0x0280 + ((n) * 4))
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#define IMPMBD(n) (0x02c0 + ((n) * 4))
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#define IMUCTR(n) (0x0300 + ((n) * 16))
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#define IMUCTR_FIXADDEN (1 << 31)
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#define IMUCTR_FIXADD_MASK (0xff << 16)
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#define IMUCTR_FIXADD_SHIFT 16
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#define IMUCTR_TTSEL_MMU(n) ((n) << 4)
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#define IMUCTR_TTSEL_PMB (8 << 4)
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#define IMUCTR_TTSEL_MASK (15 << 4)
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#define IMUCTR_FLUSH (1 << 1)
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#define IMUCTR_MMUEN (1 << 0)
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#define IMUASID(n) (0x0308 + ((n) * 16))
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#define IMUASID_ASID8_MASK (0xff << 8)
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#define IMUASID_ASID8_SHIFT 8
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#define IMUASID_ASID0_MASK (0xff << 0)
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#define IMUASID_ASID0_SHIFT 0
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/* -----------------------------------------------------------------------------
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* Read/Write Access
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*/
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static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset)
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{
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return ioread32(mmu->base + offset);
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}
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static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
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u32 data)
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{
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iowrite32(data, mmu->base + offset);
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}
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static u32 ipmmu_ctx_read(struct ipmmu_vmsa_domain *domain, unsigned int reg)
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{
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return ipmmu_read(domain->mmu, domain->context_id * IM_CTX_SIZE + reg);
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}
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static void ipmmu_ctx_write(struct ipmmu_vmsa_domain *domain, unsigned int reg,
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u32 data)
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{
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ipmmu_write(domain->mmu, domain->context_id * IM_CTX_SIZE + reg, data);
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}
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/* -----------------------------------------------------------------------------
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* TLB and microTLB Management
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*/
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/* Wait for any pending TLB invalidations to complete */
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static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
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{
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unsigned int count = 0;
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while (ipmmu_ctx_read(domain, IMCTR) & IMCTR_FLUSH) {
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cpu_relax();
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if (++count == TLB_LOOP_TIMEOUT) {
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dev_err_ratelimited(domain->mmu->dev,
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"TLB sync timed out -- MMU may be deadlocked\n");
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return;
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}
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udelay(1);
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}
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}
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static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
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{
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u32 reg;
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reg = ipmmu_ctx_read(domain, IMCTR);
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reg |= IMCTR_FLUSH;
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ipmmu_ctx_write(domain, IMCTR, reg);
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ipmmu_tlb_sync(domain);
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}
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/*
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* Enable MMU translation for the microTLB.
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*/
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static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
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unsigned int utlb)
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{
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struct ipmmu_vmsa_device *mmu = domain->mmu;
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/*
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* TODO: Reference-count the microTLB as several bus masters can be
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* connected to the same microTLB.
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*/
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/* TODO: What should we set the ASID to ? */
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ipmmu_write(mmu, IMUASID(utlb), 0);
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/* TODO: Do we need to flush the microTLB ? */
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ipmmu_write(mmu, IMUCTR(utlb),
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IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH |
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IMUCTR_MMUEN);
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}
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/*
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* Disable MMU translation for the microTLB.
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*/
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static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain,
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unsigned int utlb)
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{
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struct ipmmu_vmsa_device *mmu = domain->mmu;
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ipmmu_write(mmu, IMUCTR(utlb), 0);
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}
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static void ipmmu_tlb_flush_all(void *cookie)
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{
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struct ipmmu_vmsa_domain *domain = cookie;
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ipmmu_tlb_invalidate(domain);
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}
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static void ipmmu_tlb_add_flush(unsigned long iova, size_t size,
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size_t granule, bool leaf, void *cookie)
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{
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/* The hardware doesn't support selective TLB flush. */
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}
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static struct iommu_gather_ops ipmmu_gather_ops = {
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.tlb_flush_all = ipmmu_tlb_flush_all,
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.tlb_add_flush = ipmmu_tlb_add_flush,
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.tlb_sync = ipmmu_tlb_flush_all,
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};
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/* -----------------------------------------------------------------------------
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* Domain/Context Management
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*/
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static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
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{
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u64 ttbr;
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/*
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* Allocate the page table operations.
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*
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* VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
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* access, Long-descriptor format" that the NStable bit being set in a
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* table descriptor will result in the NStable and NS bits of all child
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* entries being ignored and considered as being set. The IPMMU seems
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* not to comply with this, as it generates a secure access page fault
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* if any of the NStable and NS bits isn't set when running in
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* non-secure mode.
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*/
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domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
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domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
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domain->cfg.ias = 32;
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domain->cfg.oas = 40;
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domain->cfg.tlb = &ipmmu_gather_ops;
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/*
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* TODO: Add support for coherent walk through CCI with DVM and remove
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* cache handling. For now, delegate it to the io-pgtable code.
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*/
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domain->cfg.iommu_dev = domain->mmu->dev;
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domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
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domain);
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if (!domain->iop)
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return -EINVAL;
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/*
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* TODO: When adding support for multiple contexts, find an unused
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* context.
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*/
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domain->context_id = 0;
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/* TTBR0 */
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ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0];
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ipmmu_ctx_write(domain, IMTTLBR0, ttbr);
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ipmmu_ctx_write(domain, IMTTUBR0, ttbr >> 32);
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/*
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* TTBCR
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* We use long descriptors with inner-shareable WBWA tables and allocate
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* the whole 32-bit VA space to TTBR0.
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*/
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ipmmu_ctx_write(domain, IMTTBCR, IMTTBCR_EAE |
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IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
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IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1);
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/* MAIR0 */
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ipmmu_ctx_write(domain, IMMAIR0, domain->cfg.arm_lpae_s1_cfg.mair[0]);
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/* IMBUSCR */
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ipmmu_ctx_write(domain, IMBUSCR,
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ipmmu_ctx_read(domain, IMBUSCR) &
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~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
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/*
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* IMSTR
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* Clear all interrupt flags.
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*/
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ipmmu_ctx_write(domain, IMSTR, ipmmu_ctx_read(domain, IMSTR));
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/*
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* IMCTR
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* Enable the MMU and interrupt generation. The long-descriptor
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* translation table format doesn't use TEX remapping. Don't enable AF
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* software management as we have no use for it. Flush the TLB as
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* required when modifying the context registers.
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*/
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ipmmu_ctx_write(domain, IMCTR, IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
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return 0;
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}
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static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
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{
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/*
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* Disable the context. Flush the TLB as required when modifying the
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* context registers.
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*
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* TODO: Is TLB flush really needed ?
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*/
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ipmmu_ctx_write(domain, IMCTR, IMCTR_FLUSH);
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ipmmu_tlb_sync(domain);
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}
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/* -----------------------------------------------------------------------------
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* Fault Handling
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*/
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static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
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{
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const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
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struct ipmmu_vmsa_device *mmu = domain->mmu;
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u32 status;
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u32 iova;
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status = ipmmu_ctx_read(domain, IMSTR);
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if (!(status & err_mask))
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return IRQ_NONE;
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iova = ipmmu_ctx_read(domain, IMEAR);
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/*
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* Clear the error status flags. Unlike traditional interrupt flag
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* registers that must be cleared by writing 1, this status register
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* seems to require 0. The error address register must be read before,
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* otherwise its value will be 0.
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*/
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ipmmu_ctx_write(domain, IMSTR, 0);
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/* Log fatal errors. */
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if (status & IMSTR_MHIT)
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dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%08x\n",
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iova);
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if (status & IMSTR_ABORT)
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dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%08x\n",
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iova);
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if (!(status & (IMSTR_PF | IMSTR_TF)))
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return IRQ_NONE;
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/*
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* Try to handle page faults and translation faults.
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*
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* TODO: We need to look up the faulty device based on the I/O VA. Use
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* the IOMMU device for now.
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*/
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if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0))
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return IRQ_HANDLED;
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dev_err_ratelimited(mmu->dev,
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"Unhandled fault: status 0x%08x iova 0x%08x\n",
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status, iova);
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return IRQ_HANDLED;
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}
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static irqreturn_t ipmmu_irq(int irq, void *dev)
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{
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struct ipmmu_vmsa_device *mmu = dev;
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struct iommu_domain *io_domain;
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struct ipmmu_vmsa_domain *domain;
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if (!mmu->mapping)
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return IRQ_NONE;
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io_domain = mmu->mapping->domain;
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domain = to_vmsa_domain(io_domain);
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return ipmmu_domain_irq(domain);
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}
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/* -----------------------------------------------------------------------------
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* IOMMU Operations
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*/
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static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
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{
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struct ipmmu_vmsa_domain *domain;
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if (type != IOMMU_DOMAIN_UNMANAGED)
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return NULL;
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domain = kzalloc(sizeof(*domain), GFP_KERNEL);
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if (!domain)
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return NULL;
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spin_lock_init(&domain->lock);
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return &domain->io_domain;
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}
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static void ipmmu_domain_free(struct iommu_domain *io_domain)
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{
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struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
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/*
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* Free the domain resources. We assume that all devices have already
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* been detached.
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*/
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ipmmu_domain_destroy_context(domain);
|
|
free_io_pgtable_ops(domain->iop);
|
|
kfree(domain);
|
|
}
|
|
|
|
static int ipmmu_attach_device(struct iommu_domain *io_domain,
|
|
struct device *dev)
|
|
{
|
|
struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
|
|
struct ipmmu_vmsa_device *mmu = archdata->mmu;
|
|
struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
|
|
unsigned long flags;
|
|
unsigned int i;
|
|
int ret = 0;
|
|
|
|
if (!mmu) {
|
|
dev_err(dev, "Cannot attach to IPMMU\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
spin_lock_irqsave(&domain->lock, flags);
|
|
|
|
if (!domain->mmu) {
|
|
/* The domain hasn't been used yet, initialize it. */
|
|
domain->mmu = mmu;
|
|
ret = ipmmu_domain_init_context(domain);
|
|
} else if (domain->mmu != mmu) {
|
|
/*
|
|
* Something is wrong, we can't attach two devices using
|
|
* different IOMMUs to the same domain.
|
|
*/
|
|
dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n",
|
|
dev_name(mmu->dev), dev_name(domain->mmu->dev));
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&domain->lock, flags);
|
|
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
for (i = 0; i < archdata->num_utlbs; ++i)
|
|
ipmmu_utlb_enable(domain, archdata->utlbs[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ipmmu_detach_device(struct iommu_domain *io_domain,
|
|
struct device *dev)
|
|
{
|
|
struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
|
|
struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < archdata->num_utlbs; ++i)
|
|
ipmmu_utlb_disable(domain, archdata->utlbs[i]);
|
|
|
|
/*
|
|
* TODO: Optimize by disabling the context when no device is attached.
|
|
*/
|
|
}
|
|
|
|
static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
|
|
phys_addr_t paddr, size_t size, int prot)
|
|
{
|
|
struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
|
|
|
|
if (!domain)
|
|
return -ENODEV;
|
|
|
|
return domain->iop->map(domain->iop, iova, paddr, size, prot);
|
|
}
|
|
|
|
static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
|
|
size_t size)
|
|
{
|
|
struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
|
|
|
|
return domain->iop->unmap(domain->iop, iova, size);
|
|
}
|
|
|
|
static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
|
|
dma_addr_t iova)
|
|
{
|
|
struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
|
|
|
|
/* TODO: Is locking needed ? */
|
|
|
|
return domain->iop->iova_to_phys(domain->iop, iova);
|
|
}
|
|
|
|
static int ipmmu_find_utlbs(struct ipmmu_vmsa_device *mmu, struct device *dev,
|
|
unsigned int *utlbs, unsigned int num_utlbs)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < num_utlbs; ++i) {
|
|
struct of_phandle_args args;
|
|
int ret;
|
|
|
|
ret = of_parse_phandle_with_args(dev->of_node, "iommus",
|
|
"#iommu-cells", i, &args);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
of_node_put(args.np);
|
|
|
|
if (args.np != mmu->dev->of_node || args.args_count != 1)
|
|
return -EINVAL;
|
|
|
|
utlbs[i] = args.args[0];
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ipmmu_add_device(struct device *dev)
|
|
{
|
|
struct ipmmu_vmsa_archdata *archdata;
|
|
struct ipmmu_vmsa_device *mmu;
|
|
struct iommu_group *group = NULL;
|
|
unsigned int *utlbs;
|
|
unsigned int i;
|
|
int num_utlbs;
|
|
int ret = -ENODEV;
|
|
|
|
if (dev->archdata.iommu) {
|
|
dev_warn(dev, "IOMMU driver already assigned to device %s\n",
|
|
dev_name(dev));
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Find the master corresponding to the device. */
|
|
|
|
num_utlbs = of_count_phandle_with_args(dev->of_node, "iommus",
|
|
"#iommu-cells");
|
|
if (num_utlbs < 0)
|
|
return -ENODEV;
|
|
|
|
utlbs = kcalloc(num_utlbs, sizeof(*utlbs), GFP_KERNEL);
|
|
if (!utlbs)
|
|
return -ENOMEM;
|
|
|
|
spin_lock(&ipmmu_devices_lock);
|
|
|
|
list_for_each_entry(mmu, &ipmmu_devices, list) {
|
|
ret = ipmmu_find_utlbs(mmu, dev, utlbs, num_utlbs);
|
|
if (!ret) {
|
|
/*
|
|
* TODO Take a reference to the MMU to protect
|
|
* against device removal.
|
|
*/
|
|
break;
|
|
}
|
|
}
|
|
|
|
spin_unlock(&ipmmu_devices_lock);
|
|
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
for (i = 0; i < num_utlbs; ++i) {
|
|
if (utlbs[i] >= mmu->num_utlbs) {
|
|
ret = -EINVAL;
|
|
goto error;
|
|
}
|
|
}
|
|
|
|
/* Create a device group and add the device to it. */
|
|
group = iommu_group_alloc();
|
|
if (IS_ERR(group)) {
|
|
dev_err(dev, "Failed to allocate IOMMU group\n");
|
|
ret = PTR_ERR(group);
|
|
goto error;
|
|
}
|
|
|
|
ret = iommu_group_add_device(group, dev);
|
|
iommu_group_put(group);
|
|
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to add device to IPMMU group\n");
|
|
group = NULL;
|
|
goto error;
|
|
}
|
|
|
|
archdata = kzalloc(sizeof(*archdata), GFP_KERNEL);
|
|
if (!archdata) {
|
|
ret = -ENOMEM;
|
|
goto error;
|
|
}
|
|
|
|
archdata->mmu = mmu;
|
|
archdata->utlbs = utlbs;
|
|
archdata->num_utlbs = num_utlbs;
|
|
dev->archdata.iommu = archdata;
|
|
|
|
/*
|
|
* Create the ARM mapping, used by the ARM DMA mapping core to allocate
|
|
* VAs. This will allocate a corresponding IOMMU domain.
|
|
*
|
|
* TODO:
|
|
* - Create one mapping per context (TLB).
|
|
* - Make the mapping size configurable ? We currently use a 2GB mapping
|
|
* at a 1GB offset to ensure that NULL VAs will fault.
|
|
*/
|
|
if (!mmu->mapping) {
|
|
struct dma_iommu_mapping *mapping;
|
|
|
|
mapping = arm_iommu_create_mapping(&platform_bus_type,
|
|
SZ_1G, SZ_2G);
|
|
if (IS_ERR(mapping)) {
|
|
dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
|
|
ret = PTR_ERR(mapping);
|
|
goto error;
|
|
}
|
|
|
|
mmu->mapping = mapping;
|
|
}
|
|
|
|
/* Attach the ARM VA mapping to the device. */
|
|
ret = arm_iommu_attach_device(dev, mmu->mapping);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to attach device to VA mapping\n");
|
|
goto error;
|
|
}
|
|
|
|
return 0;
|
|
|
|
error:
|
|
arm_iommu_release_mapping(mmu->mapping);
|
|
|
|
kfree(dev->archdata.iommu);
|
|
kfree(utlbs);
|
|
|
|
dev->archdata.iommu = NULL;
|
|
|
|
if (!IS_ERR_OR_NULL(group))
|
|
iommu_group_remove_device(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void ipmmu_remove_device(struct device *dev)
|
|
{
|
|
struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
|
|
|
|
arm_iommu_detach_device(dev);
|
|
iommu_group_remove_device(dev);
|
|
|
|
kfree(archdata->utlbs);
|
|
kfree(archdata);
|
|
|
|
dev->archdata.iommu = NULL;
|
|
}
|
|
|
|
static const struct iommu_ops ipmmu_ops = {
|
|
.domain_alloc = ipmmu_domain_alloc,
|
|
.domain_free = ipmmu_domain_free,
|
|
.attach_dev = ipmmu_attach_device,
|
|
.detach_dev = ipmmu_detach_device,
|
|
.map = ipmmu_map,
|
|
.unmap = ipmmu_unmap,
|
|
.map_sg = default_iommu_map_sg,
|
|
.iova_to_phys = ipmmu_iova_to_phys,
|
|
.add_device = ipmmu_add_device,
|
|
.remove_device = ipmmu_remove_device,
|
|
.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Probe/remove and init
|
|
*/
|
|
|
|
static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
|
|
{
|
|
unsigned int i;
|
|
|
|
/* Disable all contexts. */
|
|
for (i = 0; i < 4; ++i)
|
|
ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0);
|
|
}
|
|
|
|
static int ipmmu_probe(struct platform_device *pdev)
|
|
{
|
|
struct ipmmu_vmsa_device *mmu;
|
|
struct resource *res;
|
|
int irq;
|
|
int ret;
|
|
|
|
if (!IS_ENABLED(CONFIG_OF) && !pdev->dev.platform_data) {
|
|
dev_err(&pdev->dev, "missing platform data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL);
|
|
if (!mmu) {
|
|
dev_err(&pdev->dev, "cannot allocate device data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
mmu->dev = &pdev->dev;
|
|
mmu->num_utlbs = 32;
|
|
|
|
/* Map I/O memory and request IRQ. */
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
mmu->base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(mmu->base))
|
|
return PTR_ERR(mmu->base);
|
|
|
|
/*
|
|
* The IPMMU has two register banks, for secure and non-secure modes.
|
|
* The bank mapped at the beginning of the IPMMU address space
|
|
* corresponds to the running mode of the CPU. When running in secure
|
|
* mode the non-secure register bank is also available at an offset.
|
|
*
|
|
* Secure mode operation isn't clearly documented and is thus currently
|
|
* not implemented in the driver. Furthermore, preliminary tests of
|
|
* non-secure operation with the main register bank were not successful.
|
|
* Offset the registers base unconditionally to point to the non-secure
|
|
* alias space for now.
|
|
*/
|
|
mmu->base += IM_NS_ALIAS_OFFSET;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "no IRQ found\n");
|
|
return irq;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
|
|
dev_name(&pdev->dev), mmu);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
|
|
return ret;
|
|
}
|
|
|
|
ipmmu_device_reset(mmu);
|
|
|
|
/*
|
|
* We can't create the ARM mapping here as it requires the bus to have
|
|
* an IOMMU, which only happens when bus_set_iommu() is called in
|
|
* ipmmu_init() after the probe function returns.
|
|
*/
|
|
|
|
spin_lock(&ipmmu_devices_lock);
|
|
list_add(&mmu->list, &ipmmu_devices);
|
|
spin_unlock(&ipmmu_devices_lock);
|
|
|
|
platform_set_drvdata(pdev, mmu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ipmmu_remove(struct platform_device *pdev)
|
|
{
|
|
struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev);
|
|
|
|
spin_lock(&ipmmu_devices_lock);
|
|
list_del(&mmu->list);
|
|
spin_unlock(&ipmmu_devices_lock);
|
|
|
|
arm_iommu_release_mapping(mmu->mapping);
|
|
|
|
ipmmu_device_reset(mmu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id ipmmu_of_ids[] = {
|
|
{ .compatible = "renesas,ipmmu-vmsa", },
|
|
{ }
|
|
};
|
|
|
|
static struct platform_driver ipmmu_driver = {
|
|
.driver = {
|
|
.name = "ipmmu-vmsa",
|
|
.of_match_table = of_match_ptr(ipmmu_of_ids),
|
|
},
|
|
.probe = ipmmu_probe,
|
|
.remove = ipmmu_remove,
|
|
};
|
|
|
|
static int __init ipmmu_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = platform_driver_register(&ipmmu_driver);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (!iommu_present(&platform_bus_type))
|
|
bus_set_iommu(&platform_bus_type, &ipmmu_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit ipmmu_exit(void)
|
|
{
|
|
return platform_driver_unregister(&ipmmu_driver);
|
|
}
|
|
|
|
subsys_initcall(ipmmu_init);
|
|
module_exit(ipmmu_exit);
|
|
|
|
MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU");
|
|
MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
|
|
MODULE_LICENSE("GPL v2");
|