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![Luis de Bethencourt](/assets/img/avatar_default.png)
This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
427 lines
12 KiB
C
427 lines
12 KiB
C
/*
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* TI AEMIF driver
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*
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* Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
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*
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* Authors:
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* Murali Karicheri <m-karicheri2@ti.com>
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* Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#define TA_SHIFT 2
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#define RHOLD_SHIFT 4
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#define RSTROBE_SHIFT 7
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#define RSETUP_SHIFT 13
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#define WHOLD_SHIFT 17
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#define WSTROBE_SHIFT 20
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#define WSETUP_SHIFT 26
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#define EW_SHIFT 30
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#define SS_SHIFT 31
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#define TA(x) ((x) << TA_SHIFT)
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#define RHOLD(x) ((x) << RHOLD_SHIFT)
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#define RSTROBE(x) ((x) << RSTROBE_SHIFT)
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#define RSETUP(x) ((x) << RSETUP_SHIFT)
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#define WHOLD(x) ((x) << WHOLD_SHIFT)
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#define WSTROBE(x) ((x) << WSTROBE_SHIFT)
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#define WSETUP(x) ((x) << WSETUP_SHIFT)
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#define EW(x) ((x) << EW_SHIFT)
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#define SS(x) ((x) << SS_SHIFT)
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#define ASIZE_MAX 0x1
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#define TA_MAX 0x3
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#define RHOLD_MAX 0x7
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#define RSTROBE_MAX 0x3f
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#define RSETUP_MAX 0xf
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#define WHOLD_MAX 0x7
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#define WSTROBE_MAX 0x3f
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#define WSETUP_MAX 0xf
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#define EW_MAX 0x1
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#define SS_MAX 0x1
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#define NUM_CS 4
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#define TA_VAL(x) (((x) & TA(TA_MAX)) >> TA_SHIFT)
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#define RHOLD_VAL(x) (((x) & RHOLD(RHOLD_MAX)) >> RHOLD_SHIFT)
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#define RSTROBE_VAL(x) (((x) & RSTROBE(RSTROBE_MAX)) >> RSTROBE_SHIFT)
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#define RSETUP_VAL(x) (((x) & RSETUP(RSETUP_MAX)) >> RSETUP_SHIFT)
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#define WHOLD_VAL(x) (((x) & WHOLD(WHOLD_MAX)) >> WHOLD_SHIFT)
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#define WSTROBE_VAL(x) (((x) & WSTROBE(WSTROBE_MAX)) >> WSTROBE_SHIFT)
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#define WSETUP_VAL(x) (((x) & WSETUP(WSETUP_MAX)) >> WSETUP_SHIFT)
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#define EW_VAL(x) (((x) & EW(EW_MAX)) >> EW_SHIFT)
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#define SS_VAL(x) (((x) & SS(SS_MAX)) >> SS_SHIFT)
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#define NRCSR_OFFSET 0x00
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#define AWCCR_OFFSET 0x04
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#define A1CR_OFFSET 0x10
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#define ACR_ASIZE_MASK 0x3
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#define ACR_EW_MASK BIT(30)
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#define ACR_SS_MASK BIT(31)
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#define ASIZE_16BIT 1
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#define CONFIG_MASK (TA(TA_MAX) | \
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RHOLD(RHOLD_MAX) | \
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RSTROBE(RSTROBE_MAX) | \
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RSETUP(RSETUP_MAX) | \
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WHOLD(WHOLD_MAX) | \
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WSTROBE(WSTROBE_MAX) | \
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WSETUP(WSETUP_MAX) | \
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EW(EW_MAX) | SS(SS_MAX) | \
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ASIZE_MAX)
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/**
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* struct aemif_cs_data: structure to hold cs parameters
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* @cs: chip-select number
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* @wstrobe: write strobe width, ns
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* @rstrobe: read strobe width, ns
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* @wsetup: write setup width, ns
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* @whold: write hold width, ns
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* @rsetup: read setup width, ns
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* @rhold: read hold width, ns
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* @ta: minimum turn around time, ns
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* @enable_ss: enable/disable select strobe mode
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* @enable_ew: enable/disable extended wait mode
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* @asize: width of the asynchronous device's data bus
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*/
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struct aemif_cs_data {
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u8 cs;
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u16 wstrobe;
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u16 rstrobe;
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u8 wsetup;
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u8 whold;
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u8 rsetup;
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u8 rhold;
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u8 ta;
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u8 enable_ss;
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u8 enable_ew;
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u8 asize;
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};
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/**
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* struct aemif_device: structure to hold device data
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* @base: base address of AEMIF registers
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* @clk: source clock
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* @clk_rate: clock's rate in kHz
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* @num_cs: number of assigned chip-selects
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* @cs_offset: start number of cs nodes
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* @cs_data: array of chip-select settings
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*/
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struct aemif_device {
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void __iomem *base;
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struct clk *clk;
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unsigned long clk_rate;
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u8 num_cs;
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int cs_offset;
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struct aemif_cs_data cs_data[NUM_CS];
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};
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/**
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* aemif_calc_rate - calculate timing data.
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* @pdev: platform device to calculate for
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* @wanted: The cycle time needed in nanoseconds.
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* @clk: The input clock rate in kHz.
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* @max: The maximum divider value that can be programmed.
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*
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* On success, returns the calculated timing value minus 1 for easy
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* programming into AEMIF timing registers, else negative errno.
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*/
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static int aemif_calc_rate(struct platform_device *pdev, int wanted,
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unsigned long clk, int max)
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{
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int result;
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result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1;
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dev_dbg(&pdev->dev, "%s: result %d from %ld, %d\n", __func__, result,
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clk, wanted);
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/* It is generally OK to have a more relaxed timing than requested... */
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if (result < 0)
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result = 0;
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/* ... But configuring tighter timings is not an option. */
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else if (result > max)
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result = -EINVAL;
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return result;
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}
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/**
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* aemif_config_abus - configure async bus parameters
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* @pdev: platform device to configure for
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* @csnum: aemif chip select number
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*
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* This function programs the given timing values (in real clock) into the
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* AEMIF registers taking the AEMIF clock into account.
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*
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* This function does not use any locking while programming the AEMIF
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* because it is expected that there is only one user of a given
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* chip-select.
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*
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* Returns 0 on success, else negative errno.
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*/
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static int aemif_config_abus(struct platform_device *pdev, int csnum)
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{
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struct aemif_device *aemif = platform_get_drvdata(pdev);
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struct aemif_cs_data *data = &aemif->cs_data[csnum];
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int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
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unsigned long clk_rate = aemif->clk_rate;
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unsigned offset;
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u32 set, val;
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offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
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ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX);
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rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX);
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rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX);
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rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX);
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whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX);
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wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX);
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wsetup = aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX);
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if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 ||
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whold < 0 || wstrobe < 0 || wsetup < 0) {
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dev_err(&pdev->dev, "%s: cannot get suitable timings\n",
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__func__);
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return -EINVAL;
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}
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set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) |
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WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup);
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set |= (data->asize & ACR_ASIZE_MASK);
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if (data->enable_ew)
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set |= ACR_EW_MASK;
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if (data->enable_ss)
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set |= ACR_SS_MASK;
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val = readl(aemif->base + offset);
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val &= ~CONFIG_MASK;
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val |= set;
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writel(val, aemif->base + offset);
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return 0;
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}
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static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate)
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{
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return ((val + 1) * NSEC_PER_MSEC) / clk_rate;
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}
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/**
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* aemif_get_hw_params - function to read hw register values
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* @pdev: platform device to read for
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* @csnum: aemif chip select number
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*
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* This function reads the defaults from the registers and update
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* the timing values. Required for get/set commands and also for
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* the case when driver needs to use defaults in hardware.
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*/
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static void aemif_get_hw_params(struct platform_device *pdev, int csnum)
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{
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struct aemif_device *aemif = platform_get_drvdata(pdev);
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struct aemif_cs_data *data = &aemif->cs_data[csnum];
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unsigned long clk_rate = aemif->clk_rate;
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u32 val, offset;
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offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4;
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val = readl(aemif->base + offset);
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data->ta = aemif_cycles_to_nsec(TA_VAL(val), clk_rate);
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data->rhold = aemif_cycles_to_nsec(RHOLD_VAL(val), clk_rate);
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data->rstrobe = aemif_cycles_to_nsec(RSTROBE_VAL(val), clk_rate);
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data->rsetup = aemif_cycles_to_nsec(RSETUP_VAL(val), clk_rate);
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data->whold = aemif_cycles_to_nsec(WHOLD_VAL(val), clk_rate);
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data->wstrobe = aemif_cycles_to_nsec(WSTROBE_VAL(val), clk_rate);
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data->wsetup = aemif_cycles_to_nsec(WSETUP_VAL(val), clk_rate);
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data->enable_ew = EW_VAL(val);
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data->enable_ss = SS_VAL(val);
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data->asize = val & ASIZE_MAX;
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}
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/**
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* of_aemif_parse_abus_config - parse CS configuration from DT
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* @pdev: platform device to parse for
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* @np: device node ptr
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*
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* This function update the emif async bus configuration based on the values
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* configured in a cs device binding node.
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*/
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static int of_aemif_parse_abus_config(struct platform_device *pdev,
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struct device_node *np)
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{
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struct aemif_device *aemif = platform_get_drvdata(pdev);
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struct aemif_cs_data *data;
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u32 cs;
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u32 val;
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if (of_property_read_u32(np, "ti,cs-chipselect", &cs)) {
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dev_dbg(&pdev->dev, "cs property is required");
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return -EINVAL;
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}
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if (cs - aemif->cs_offset >= NUM_CS || cs < aemif->cs_offset) {
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dev_dbg(&pdev->dev, "cs number is incorrect %d", cs);
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return -EINVAL;
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}
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if (aemif->num_cs >= NUM_CS) {
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dev_dbg(&pdev->dev, "cs count is more than %d", NUM_CS);
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return -EINVAL;
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}
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data = &aemif->cs_data[aemif->num_cs];
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data->cs = cs;
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/* read the current value in the hw register */
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aemif_get_hw_params(pdev, aemif->num_cs++);
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/* override the values from device node */
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if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val))
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data->ta = val;
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if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val))
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data->rhold = val;
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if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val))
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data->rstrobe = val;
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if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val))
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data->rsetup = val;
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if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val))
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data->whold = val;
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if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val))
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data->wstrobe = val;
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if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val))
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data->wsetup = val;
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if (!of_property_read_u32(np, "ti,cs-bus-width", &val))
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if (val == 16)
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data->asize = 1;
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data->enable_ew = of_property_read_bool(np, "ti,cs-extended-wait-mode");
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data->enable_ss = of_property_read_bool(np, "ti,cs-select-strobe-mode");
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return 0;
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}
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static const struct of_device_id aemif_of_match[] = {
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{ .compatible = "ti,davinci-aemif", },
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{ .compatible = "ti,da850-aemif", },
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{},
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};
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MODULE_DEVICE_TABLE(of, aemif_of_match);
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static int aemif_probe(struct platform_device *pdev)
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{
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int i;
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int ret = -ENODEV;
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct device_node *child_np;
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struct aemif_device *aemif;
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if (np == NULL)
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return 0;
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aemif = devm_kzalloc(dev, sizeof(*aemif), GFP_KERNEL);
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if (!aemif)
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return -ENOMEM;
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platform_set_drvdata(pdev, aemif);
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aemif->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(aemif->clk)) {
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dev_err(dev, "cannot get clock 'aemif'\n");
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return PTR_ERR(aemif->clk);
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}
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clk_prepare_enable(aemif->clk);
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aemif->clk_rate = clk_get_rate(aemif->clk) / MSEC_PER_SEC;
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if (of_device_is_compatible(np, "ti,da850-aemif"))
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aemif->cs_offset = 2;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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aemif->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(aemif->base)) {
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ret = PTR_ERR(aemif->base);
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goto error;
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}
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/*
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* For every controller device node, there is a cs device node that
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* describe the bus configuration parameters. This functions iterate
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* over these nodes and update the cs data array.
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*/
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for_each_available_child_of_node(np, child_np) {
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ret = of_aemif_parse_abus_config(pdev, child_np);
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if (ret < 0)
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goto error;
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}
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for (i = 0; i < aemif->num_cs; i++) {
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ret = aemif_config_abus(pdev, i);
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if (ret < 0) {
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dev_err(dev, "Error configuring chip select %d\n",
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aemif->cs_data[i].cs);
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goto error;
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}
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}
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/*
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* Create a child devices explicitly from here to
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* guarantee that the child will be probed after the AEMIF timing
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* parameters are set.
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*/
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for_each_available_child_of_node(np, child_np) {
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ret = of_platform_populate(child_np, NULL, NULL, dev);
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if (ret < 0)
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goto error;
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}
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return 0;
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error:
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clk_disable_unprepare(aemif->clk);
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return ret;
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}
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static int aemif_remove(struct platform_device *pdev)
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{
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struct aemif_device *aemif = platform_get_drvdata(pdev);
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clk_disable_unprepare(aemif->clk);
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return 0;
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}
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static struct platform_driver aemif_driver = {
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.probe = aemif_probe,
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.remove = aemif_remove,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = of_match_ptr(aemif_of_match),
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},
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};
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module_platform_driver(aemif_driver);
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MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
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MODULE_AUTHOR("Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>");
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MODULE_DESCRIPTION("Texas Instruments AEMIF driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" KBUILD_MODNAME);
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