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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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0a41b0c5d9
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
577 lines
15 KiB
C
577 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* PWM controller driver for Amlogic Meson SoCs.
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*
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* This PWM is only a set of Gates, Dividers and Counters:
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* PWM output is achieved by calculating a clock that permits calculating
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* two periods (low and high). The counter then has to be set to switch after
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* N cycles for the first half period.
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* The hardware has no "polarity" setting. This driver reverses the period
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* cycles (the low length is inverted with the high length) for
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* PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
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* from the hardware.
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* Setting the duty cycle will disable and re-enable the PWM output.
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* Disabling the PWM stops the output immediately (without waiting for the
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* current period to complete first).
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*
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* The public S912 (GXM) datasheet contains some documentation for this PWM
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* controller starting on page 543:
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* https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
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* An updated version of this IP block is found in S922X (G12B) SoCs. The
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* datasheet contains the description for this IP block revision starting at
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* page 1084:
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* https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2014 Amlogic, Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define REG_PWM_A 0x0
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#define REG_PWM_B 0x4
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#define PWM_LOW_MASK GENMASK(15, 0)
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#define PWM_HIGH_MASK GENMASK(31, 16)
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#define REG_MISC_AB 0x8
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#define MISC_B_CLK_EN_SHIFT 23
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#define MISC_A_CLK_EN_SHIFT 15
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#define MISC_CLK_DIV_WIDTH 7
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#define MISC_B_CLK_DIV_SHIFT 16
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#define MISC_A_CLK_DIV_SHIFT 8
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#define MISC_B_CLK_SEL_SHIFT 6
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#define MISC_A_CLK_SEL_SHIFT 4
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#define MISC_CLK_SEL_MASK 0x3
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#define MISC_B_EN BIT(1)
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#define MISC_A_EN BIT(0)
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#define MESON_NUM_PWMS 2
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#define MESON_MAX_MUX_PARENTS 4
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static struct meson_pwm_channel_data {
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u8 reg_offset;
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u8 clk_sel_shift;
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u8 clk_div_shift;
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u8 clk_en_shift;
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u32 pwm_en_mask;
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} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
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{
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.reg_offset = REG_PWM_A,
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.clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
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.clk_div_shift = MISC_A_CLK_DIV_SHIFT,
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.clk_en_shift = MISC_A_CLK_EN_SHIFT,
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.pwm_en_mask = MISC_A_EN,
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},
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{
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.reg_offset = REG_PWM_B,
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.clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
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.clk_div_shift = MISC_B_CLK_DIV_SHIFT,
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.clk_en_shift = MISC_B_CLK_EN_SHIFT,
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.pwm_en_mask = MISC_B_EN,
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}
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};
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struct meson_pwm_channel {
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unsigned long rate;
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unsigned int hi;
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unsigned int lo;
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struct clk_mux mux;
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struct clk_divider div;
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struct clk_gate gate;
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struct clk *clk;
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};
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struct meson_pwm_data {
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const char * const *parent_names;
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unsigned int num_parents;
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};
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struct meson_pwm {
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struct pwm_chip chip;
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const struct meson_pwm_data *data;
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struct meson_pwm_channel channels[MESON_NUM_PWMS];
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void __iomem *base;
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/*
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* Protects register (write) access to the REG_MISC_AB register
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* that is shared between the two PWMs.
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*/
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spinlock_t lock;
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};
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static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
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{
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return container_of(chip, struct meson_pwm, chip);
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}
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static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct meson_pwm *meson = to_meson_pwm(chip);
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struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
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struct device *dev = chip->dev;
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int err;
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err = clk_prepare_enable(channel->clk);
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if (err < 0) {
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dev_err(dev, "failed to enable clock %s: %d\n",
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__clk_get_name(channel->clk), err);
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return err;
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}
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return 0;
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}
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static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct meson_pwm *meson = to_meson_pwm(chip);
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struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
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clk_disable_unprepare(channel->clk);
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}
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static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
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unsigned int cnt, duty_cnt;
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unsigned long fin_freq;
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u64 duty, period, freq;
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duty = state->duty_cycle;
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period = state->period;
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/*
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* Note this is wrong. The result is an output wave that isn't really
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* inverted and so is wrongly identified by .get_state as normal.
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* Fixing this needs some care however as some machines might rely on
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* this.
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*/
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if (state->polarity == PWM_POLARITY_INVERSED)
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duty = period - duty;
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freq = div64_u64(NSEC_PER_SEC * 0xffffULL, period);
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if (freq > ULONG_MAX)
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freq = ULONG_MAX;
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fin_freq = clk_round_rate(channel->clk, freq);
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if (fin_freq == 0) {
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dev_err(meson->chip.dev, "invalid source clock frequency\n");
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return -EINVAL;
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}
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dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
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cnt = div_u64(fin_freq * period, NSEC_PER_SEC);
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if (cnt > 0xffff) {
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dev_err(meson->chip.dev, "unable to get period cnt\n");
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return -EINVAL;
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}
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dev_dbg(meson->chip.dev, "period=%llu cnt=%u\n", period, cnt);
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if (duty == period) {
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channel->hi = cnt;
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channel->lo = 0;
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} else if (duty == 0) {
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channel->hi = 0;
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channel->lo = cnt;
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} else {
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duty_cnt = div_u64(fin_freq * duty, NSEC_PER_SEC);
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dev_dbg(meson->chip.dev, "duty=%llu duty_cnt=%u\n", duty, duty_cnt);
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channel->hi = duty_cnt;
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channel->lo = cnt - duty_cnt;
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}
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channel->rate = fin_freq;
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return 0;
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}
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static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
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{
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struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
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struct meson_pwm_channel_data *channel_data;
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unsigned long flags;
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u32 value;
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int err;
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channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
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err = clk_set_rate(channel->clk, channel->rate);
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if (err)
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dev_err(meson->chip.dev, "setting clock rate failed\n");
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spin_lock_irqsave(&meson->lock, flags);
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value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
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FIELD_PREP(PWM_LOW_MASK, channel->lo);
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writel(value, meson->base + channel_data->reg_offset);
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value = readl(meson->base + REG_MISC_AB);
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value |= channel_data->pwm_en_mask;
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writel(value, meson->base + REG_MISC_AB);
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spin_unlock_irqrestore(&meson->lock, flags);
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}
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static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
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{
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&meson->lock, flags);
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value = readl(meson->base + REG_MISC_AB);
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value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
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writel(value, meson->base + REG_MISC_AB);
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spin_unlock_irqrestore(&meson->lock, flags);
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}
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static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct meson_pwm *meson = to_meson_pwm(chip);
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struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
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int err = 0;
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if (!state->enabled) {
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if (state->polarity == PWM_POLARITY_INVERSED) {
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/*
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* This IP block revision doesn't have an "always high"
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* setting which we can use for "inverted disabled".
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* Instead we achieve this by setting mux parent with
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* highest rate and minimum divider value, resulting
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* in the shortest possible duration for one "count"
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* and "period == duty_cycle". This results in a signal
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* which is LOW for one "count", while being HIGH for
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* the rest of the (so the signal is HIGH for slightly
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* less than 100% of the period, but this is the best
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* we can achieve).
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*/
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channel->rate = ULONG_MAX;
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channel->hi = ~0;
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channel->lo = 0;
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meson_pwm_enable(meson, pwm);
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} else {
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meson_pwm_disable(meson, pwm);
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}
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} else {
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err = meson_pwm_calc(meson, pwm, state);
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if (err < 0)
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return err;
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meson_pwm_enable(meson, pwm);
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}
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return 0;
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}
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static u64 meson_pwm_cnt_to_ns(struct pwm_chip *chip, struct pwm_device *pwm,
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u32 cnt)
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{
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struct meson_pwm *meson = to_meson_pwm(chip);
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struct meson_pwm_channel *channel;
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unsigned long fin_freq;
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/* to_meson_pwm() can only be used after .get_state() is called */
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channel = &meson->channels[pwm->hwpwm];
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fin_freq = clk_get_rate(channel->clk);
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if (fin_freq == 0)
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return 0;
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return div64_ul(NSEC_PER_SEC * (u64)cnt, fin_freq);
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}
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static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct meson_pwm *meson = to_meson_pwm(chip);
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struct meson_pwm_channel_data *channel_data;
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struct meson_pwm_channel *channel;
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u32 value;
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if (!state)
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return 0;
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channel = &meson->channels[pwm->hwpwm];
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channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
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value = readl(meson->base + REG_MISC_AB);
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state->enabled = value & channel_data->pwm_en_mask;
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value = readl(meson->base + channel_data->reg_offset);
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channel->lo = FIELD_GET(PWM_LOW_MASK, value);
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channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
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state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->lo + channel->hi);
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state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
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state->polarity = PWM_POLARITY_NORMAL;
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return 0;
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}
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static const struct pwm_ops meson_pwm_ops = {
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.request = meson_pwm_request,
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.free = meson_pwm_free,
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.apply = meson_pwm_apply,
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.get_state = meson_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static const char * const pwm_meson8b_parent_names[] = {
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"xtal", NULL, "fclk_div4", "fclk_div3"
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};
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static const struct meson_pwm_data pwm_meson8b_data = {
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.parent_names = pwm_meson8b_parent_names,
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.num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
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};
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/*
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* Only the 2 first inputs of the GXBB AO PWMs are valid
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* The last 2 are grounded
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*/
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static const char * const pwm_gxbb_ao_parent_names[] = {
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"xtal", "clk81"
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};
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static const struct meson_pwm_data pwm_gxbb_ao_data = {
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.parent_names = pwm_gxbb_ao_parent_names,
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.num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
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};
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static const char * const pwm_axg_ee_parent_names[] = {
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"xtal", "fclk_div5", "fclk_div4", "fclk_div3"
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};
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static const struct meson_pwm_data pwm_axg_ee_data = {
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.parent_names = pwm_axg_ee_parent_names,
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.num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
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};
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static const char * const pwm_axg_ao_parent_names[] = {
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"xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5"
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};
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static const struct meson_pwm_data pwm_axg_ao_data = {
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.parent_names = pwm_axg_ao_parent_names,
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.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
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};
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static const char * const pwm_g12a_ao_ab_parent_names[] = {
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"xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5"
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};
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static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
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.parent_names = pwm_g12a_ao_ab_parent_names,
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.num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
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};
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static const char * const pwm_g12a_ao_cd_parent_names[] = {
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"xtal", "g12a_ao_clk81",
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};
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static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
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.parent_names = pwm_g12a_ao_cd_parent_names,
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.num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
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};
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static const struct of_device_id meson_pwm_matches[] = {
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{
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.compatible = "amlogic,meson8b-pwm",
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.data = &pwm_meson8b_data
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},
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{
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.compatible = "amlogic,meson-gxbb-pwm",
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.data = &pwm_meson8b_data
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},
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{
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.compatible = "amlogic,meson-gxbb-ao-pwm",
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.data = &pwm_gxbb_ao_data
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},
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{
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.compatible = "amlogic,meson-axg-ee-pwm",
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.data = &pwm_axg_ee_data
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},
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{
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.compatible = "amlogic,meson-axg-ao-pwm",
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.data = &pwm_axg_ao_data
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},
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{
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.compatible = "amlogic,meson-g12a-ee-pwm",
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.data = &pwm_meson8b_data
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},
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{
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.compatible = "amlogic,meson-g12a-ao-pwm-ab",
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.data = &pwm_g12a_ao_ab_data
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},
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{
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.compatible = "amlogic,meson-g12a-ao-pwm-cd",
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.data = &pwm_g12a_ao_cd_data
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, meson_pwm_matches);
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static int meson_pwm_init_channels(struct meson_pwm *meson)
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{
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struct clk_parent_data mux_parent_data[MESON_MAX_MUX_PARENTS] = {};
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struct device *dev = meson->chip.dev;
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unsigned int i;
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char name[255];
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int err;
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for (i = 0; i < meson->data->num_parents; i++) {
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mux_parent_data[i].index = -1;
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mux_parent_data[i].name = meson->data->parent_names[i];
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}
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for (i = 0; i < meson->chip.npwm; i++) {
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struct meson_pwm_channel *channel = &meson->channels[i];
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struct clk_parent_data div_parent = {}, gate_parent = {};
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struct clk_init_data init = {};
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snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
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init.name = name;
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init.ops = &clk_mux_ops;
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init.flags = 0;
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init.parent_data = mux_parent_data;
|
|
init.num_parents = meson->data->num_parents;
|
|
|
|
channel->mux.reg = meson->base + REG_MISC_AB;
|
|
channel->mux.shift =
|
|
meson_pwm_per_channel_data[i].clk_sel_shift;
|
|
channel->mux.mask = MISC_CLK_SEL_MASK;
|
|
channel->mux.flags = 0;
|
|
channel->mux.lock = &meson->lock;
|
|
channel->mux.table = NULL;
|
|
channel->mux.hw.init = &init;
|
|
|
|
err = devm_clk_hw_register(dev, &channel->mux.hw);
|
|
if (err) {
|
|
dev_err(dev, "failed to register %s: %d\n", name, err);
|
|
return err;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i);
|
|
|
|
init.name = name;
|
|
init.ops = &clk_divider_ops;
|
|
init.flags = CLK_SET_RATE_PARENT;
|
|
div_parent.index = -1;
|
|
div_parent.hw = &channel->mux.hw;
|
|
init.parent_data = &div_parent;
|
|
init.num_parents = 1;
|
|
|
|
channel->div.reg = meson->base + REG_MISC_AB;
|
|
channel->div.shift = meson_pwm_per_channel_data[i].clk_div_shift;
|
|
channel->div.width = MISC_CLK_DIV_WIDTH;
|
|
channel->div.hw.init = &init;
|
|
channel->div.flags = 0;
|
|
channel->div.lock = &meson->lock;
|
|
|
|
err = devm_clk_hw_register(dev, &channel->div.hw);
|
|
if (err) {
|
|
dev_err(dev, "failed to register %s: %d\n", name, err);
|
|
return err;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i);
|
|
|
|
init.name = name;
|
|
init.ops = &clk_gate_ops;
|
|
init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
|
|
gate_parent.index = -1;
|
|
gate_parent.hw = &channel->div.hw;
|
|
init.parent_data = &gate_parent;
|
|
init.num_parents = 1;
|
|
|
|
channel->gate.reg = meson->base + REG_MISC_AB;
|
|
channel->gate.bit_idx = meson_pwm_per_channel_data[i].clk_en_shift;
|
|
channel->gate.hw.init = &init;
|
|
channel->gate.flags = 0;
|
|
channel->gate.lock = &meson->lock;
|
|
|
|
err = devm_clk_hw_register(dev, &channel->gate.hw);
|
|
if (err) {
|
|
dev_err(dev, "failed to register %s: %d\n", name, err);
|
|
return err;
|
|
}
|
|
|
|
channel->clk = devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL);
|
|
if (IS_ERR(channel->clk)) {
|
|
err = PTR_ERR(channel->clk);
|
|
dev_err(dev, "failed to register %s: %d\n", name, err);
|
|
return err;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_pwm_probe(struct platform_device *pdev)
|
|
{
|
|
struct meson_pwm *meson;
|
|
int err;
|
|
|
|
meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
|
|
if (!meson)
|
|
return -ENOMEM;
|
|
|
|
meson->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(meson->base))
|
|
return PTR_ERR(meson->base);
|
|
|
|
spin_lock_init(&meson->lock);
|
|
meson->chip.dev = &pdev->dev;
|
|
meson->chip.ops = &meson_pwm_ops;
|
|
meson->chip.npwm = MESON_NUM_PWMS;
|
|
|
|
meson->data = of_device_get_match_data(&pdev->dev);
|
|
|
|
err = meson_pwm_init_channels(meson);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = devm_pwmchip_add(&pdev->dev, &meson->chip);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver meson_pwm_driver = {
|
|
.driver = {
|
|
.name = "meson-pwm",
|
|
.of_match_table = meson_pwm_matches,
|
|
},
|
|
.probe = meson_pwm_probe,
|
|
};
|
|
module_platform_driver(meson_pwm_driver);
|
|
|
|
MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
|
|
MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
|
|
MODULE_LICENSE("Dual BSD/GPL");
|