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![Oliver O'Halloran](/assets/img/avatar_default.png)
With the previous patch applied pcibios_setup_device() will always be run when pcibios_bus_add_device() is called. There are several code paths where pcibios_setup_bus_device() is still called (the PowerPC specific PCI hotplug support is one) so with just the previous patch applied the setup can be run multiple times on a device, once before the device is added to the bus and once after. There's no need to run the setup in the early case any more so just remove it entirely. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Tested-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20191028085424.12006-3-oohall@gmail.com
447 lines
13 KiB
C
447 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Helper routines to scan the device tree for PCI devices and busses
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*
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* Migrated out of PowerPC architecture pci_64.c file by Grant Likely
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* <grant.likely@secretlab.ca> so that these routines are available for
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* 32 bit also.
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*
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* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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* Rework, based on alpha PCI code.
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* Copyright (c) 2009 Secret Lab Technologies Ltd.
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*/
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#include <linux/pci.h>
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#include <linux/export.h>
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#include <asm/pci-bridge.h>
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#include <asm/prom.h>
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/**
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* get_int_prop - Decode a u32 from a device tree property
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*/
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static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
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{
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const __be32 *prop;
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int len;
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prop = of_get_property(np, name, &len);
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if (prop && len >= 4)
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return of_read_number(prop, 1);
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return def;
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}
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/**
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* pci_parse_of_flags - Parse the flags cell of a device tree PCI address
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* @addr0: value of 1st cell of a device tree PCI address.
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* @bridge: Set this flag if the address is from a bridge 'ranges' property
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*
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* PCI Bus Binding to IEEE Std 1275-1994
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*
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* Bit# 33222222 22221111 11111100 00000000
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* 10987654 32109876 54321098 76543210
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* phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
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* phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
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* phys.lo cell: llllllll llllllll llllllll llllllll
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*
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* where:
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* n is 0 if the address is relocatable, 1 otherwise
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* p is 1 if the addressable region is "prefetchable", 0 otherwise
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* t is 1 if the address is aliased (for non-relocatable I/O),
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* below 1 MB (for Memory),or below 64 KB (for relocatable I/O).
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* ss is the space code, denoting the address space:
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* 00 denotes Configuration Space
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* 01 denotes I/O Space
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* 10 denotes 32-bit-address Memory Space
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* 11 denotes 64-bit-address Memory Space
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* bbbbbbbb is the 8-bit Bus Number
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* ddddd is the 5-bit Device Number
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* fff is the 3-bit Function Number
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* rrrrrrrr is the 8-bit Register Number
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*/
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#define OF_PCI_ADDR0_SPACE(ss) (((ss)&3)<<24)
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#define OF_PCI_ADDR0_SPACE_CFG OF_PCI_ADDR0_SPACE(0)
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#define OF_PCI_ADDR0_SPACE_IO OF_PCI_ADDR0_SPACE(1)
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#define OF_PCI_ADDR0_SPACE_MMIO32 OF_PCI_ADDR0_SPACE(2)
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#define OF_PCI_ADDR0_SPACE_MMIO64 OF_PCI_ADDR0_SPACE(3)
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#define OF_PCI_ADDR0_SPACE_MASK OF_PCI_ADDR0_SPACE(3)
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#define OF_PCI_ADDR0_RELOC (1UL<<31)
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#define OF_PCI_ADDR0_PREFETCH (1UL<<30)
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#define OF_PCI_ADDR0_ALIAS (1UL<<29)
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#define OF_PCI_ADDR0_BUS 0x00FF0000UL
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#define OF_PCI_ADDR0_DEV 0x0000F800UL
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#define OF_PCI_ADDR0_FN 0x00000700UL
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#define OF_PCI_ADDR0_BARREG 0x000000FFUL
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unsigned int pci_parse_of_flags(u32 addr0, int bridge)
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{
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unsigned int flags = 0, as = addr0 & OF_PCI_ADDR0_SPACE_MASK;
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if (as == OF_PCI_ADDR0_SPACE_MMIO32 || as == OF_PCI_ADDR0_SPACE_MMIO64) {
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flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
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if (as == OF_PCI_ADDR0_SPACE_MMIO64)
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flags |= PCI_BASE_ADDRESS_MEM_TYPE_64 | IORESOURCE_MEM_64;
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if (addr0 & OF_PCI_ADDR0_ALIAS)
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flags |= PCI_BASE_ADDRESS_MEM_TYPE_1M;
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if (addr0 & OF_PCI_ADDR0_PREFETCH)
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flags |= IORESOURCE_PREFETCH |
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PCI_BASE_ADDRESS_MEM_PREFETCH;
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/* Note: We don't know whether the ROM has been left enabled
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* by the firmware or not. We mark it as disabled (ie, we do
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* not set the IORESOURCE_ROM_ENABLE flag) for now rather than
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* do a config space read, it will be force-enabled if needed
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*/
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if (!bridge && (addr0 & OF_PCI_ADDR0_BARREG) == PCI_ROM_ADDRESS)
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flags |= IORESOURCE_READONLY;
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} else if (as == OF_PCI_ADDR0_SPACE_IO)
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flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
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if (flags)
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flags |= IORESOURCE_SIZEALIGN;
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return flags;
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}
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/**
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* of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node
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* @node: device tree node for the PCI device
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* @dev: pci_dev structure for the device
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*
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* This function parses the 'assigned-addresses' property of a PCI devices'
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* device tree node and writes them into the associated pci_dev structure.
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*/
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static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
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{
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u64 base, size;
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unsigned int flags;
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struct pci_bus_region region;
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struct resource *res;
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const __be32 *addrs;
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u32 i;
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int proplen;
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bool mark_unset = false;
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addrs = of_get_property(node, "assigned-addresses", &proplen);
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if (!addrs || !proplen) {
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addrs = of_get_property(node, "reg", &proplen);
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if (!addrs || !proplen)
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return;
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mark_unset = true;
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}
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pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
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for (; proplen >= 20; proplen -= 20, addrs += 5) {
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flags = pci_parse_of_flags(of_read_number(addrs, 1), 0);
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if (!flags)
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continue;
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base = of_read_number(&addrs[1], 2);
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size = of_read_number(&addrs[3], 2);
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if (!size)
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continue;
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i = of_read_number(addrs, 1) & 0xff;
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pr_debug(" base: %llx, size: %llx, i: %x\n",
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(unsigned long long)base,
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(unsigned long long)size, i);
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if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
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res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
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} else if (i == dev->rom_base_reg) {
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res = &dev->resource[PCI_ROM_RESOURCE];
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flags |= IORESOURCE_READONLY;
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} else {
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printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
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continue;
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}
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res->flags = flags;
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if (mark_unset)
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res->flags |= IORESOURCE_UNSET;
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res->name = pci_name(dev);
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region.start = base;
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region.end = base + size - 1;
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pcibios_bus_to_resource(dev->bus, res, ®ion);
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}
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}
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/**
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* of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev
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* @node: device tree node pointer
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* @bus: bus the device is sitting on
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* @devfn: PCI function number, extracted from device tree by caller.
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*/
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struct pci_dev *of_create_pci_dev(struct device_node *node,
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struct pci_bus *bus, int devfn)
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{
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struct pci_dev *dev;
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dev = pci_alloc_dev(bus);
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if (!dev)
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return NULL;
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pr_debug(" create device, devfn: %x, type: %s\n", devfn,
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of_node_get_device_type(node));
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dev->dev.of_node = of_node_get(node);
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dev->dev.parent = bus->bridge;
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dev->dev.bus = &pci_bus_type;
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dev->devfn = devfn;
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dev->multifunction = 0; /* maybe a lie? */
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dev->needs_freset = 0; /* pcie fundamental reset required */
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set_pcie_port_type(dev);
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pci_dev_assign_slot(dev);
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dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
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dev->device = get_int_prop(node, "device-id", 0xffff);
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dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
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dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
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dev->cfg_size = pci_cfg_space_size(dev);
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dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
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dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
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dev->class = get_int_prop(node, "class-code", 0);
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dev->revision = get_int_prop(node, "revision-id", 0);
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pr_debug(" class: 0x%x\n", dev->class);
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pr_debug(" revision: 0x%x\n", dev->revision);
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dev->current_state = PCI_UNKNOWN; /* unknown power state */
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dev->error_state = pci_channel_io_normal;
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dev->dma_mask = 0xffffffff;
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/* Early fixups, before probing the BARs */
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pci_fixup_device(pci_fixup_early, dev);
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if (of_node_is_type(node, "pci") || of_node_is_type(node, "pciex")) {
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/* a PCI-PCI bridge */
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dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
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dev->rom_base_reg = PCI_ROM_ADDRESS1;
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set_pcie_hotplug_bridge(dev);
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} else if (of_node_is_type(node, "cardbus")) {
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dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
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} else {
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dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
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dev->rom_base_reg = PCI_ROM_ADDRESS;
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/* Maybe do a default OF mapping here */
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dev->irq = 0;
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}
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of_pci_parse_addrs(node, dev);
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pr_debug(" adding to system ...\n");
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pci_device_add(dev, bus);
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return dev;
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}
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EXPORT_SYMBOL(of_create_pci_dev);
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/**
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* of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
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* @dev: pci_dev structure for the bridge
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*
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* of_scan_bus() calls this routine for each PCI bridge that it finds, and
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* this routine in turn call of_scan_bus() recusively to scan for more child
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* devices.
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*/
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void of_scan_pci_bridge(struct pci_dev *dev)
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{
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struct device_node *node = dev->dev.of_node;
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struct pci_bus *bus;
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struct pci_controller *phb;
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const __be32 *busrange, *ranges;
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int len, i, mode;
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struct pci_bus_region region;
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struct resource *res;
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unsigned int flags;
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u64 size;
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pr_debug("of_scan_pci_bridge(%pOF)\n", node);
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/* parse bus-range property */
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busrange = of_get_property(node, "bus-range", &len);
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if (busrange == NULL || len != 8) {
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printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %pOF\n",
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node);
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return;
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}
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ranges = of_get_property(node, "ranges", &len);
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if (ranges == NULL) {
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printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %pOF\n",
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node);
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return;
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}
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bus = pci_find_bus(pci_domain_nr(dev->bus),
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of_read_number(busrange, 1));
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if (!bus) {
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bus = pci_add_new_bus(dev->bus, dev,
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of_read_number(busrange, 1));
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if (!bus) {
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printk(KERN_ERR "Failed to create pci bus for %pOF\n",
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node);
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return;
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}
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}
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bus->primary = dev->bus->number;
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pci_bus_insert_busn_res(bus, of_read_number(busrange, 1),
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of_read_number(busrange+1, 1));
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bus->bridge_ctl = 0;
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/* parse ranges property */
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/* PCI #address-cells == 3 and #size-cells == 2 always */
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res = &dev->resource[PCI_BRIDGE_RESOURCES];
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for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
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res->flags = 0;
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bus->resource[i] = res;
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++res;
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}
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i = 1;
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for (; len >= 32; len -= 32, ranges += 8) {
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flags = pci_parse_of_flags(of_read_number(ranges, 1), 1);
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size = of_read_number(&ranges[6], 2);
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if (flags == 0 || size == 0)
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continue;
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if (flags & IORESOURCE_IO) {
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res = bus->resource[0];
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if (res->flags) {
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printk(KERN_ERR "PCI: ignoring extra I/O range"
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" for bridge %pOF\n", node);
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continue;
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}
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} else {
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if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
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printk(KERN_ERR "PCI: too many memory ranges"
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" for bridge %pOF\n", node);
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continue;
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}
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res = bus->resource[i];
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++i;
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}
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res->flags = flags;
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region.start = of_read_number(&ranges[1], 2);
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region.end = region.start + size - 1;
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pcibios_bus_to_resource(dev->bus, res, ®ion);
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}
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sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
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bus->number);
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pr_debug(" bus name: %s\n", bus->name);
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phb = pci_bus_to_host(bus);
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mode = PCI_PROBE_NORMAL;
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if (phb->controller_ops.probe_mode)
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mode = phb->controller_ops.probe_mode(bus);
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pr_debug(" probe mode: %d\n", mode);
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if (mode == PCI_PROBE_DEVTREE)
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of_scan_bus(node, bus);
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else if (mode == PCI_PROBE_NORMAL)
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pci_scan_child_bus(bus);
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}
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EXPORT_SYMBOL(of_scan_pci_bridge);
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static struct pci_dev *of_scan_pci_dev(struct pci_bus *bus,
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struct device_node *dn)
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{
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struct pci_dev *dev = NULL;
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const __be32 *reg;
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int reglen, devfn;
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#ifdef CONFIG_EEH
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struct eeh_dev *edev = pdn_to_eeh_dev(PCI_DN(dn));
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#endif
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pr_debug(" * %pOF\n", dn);
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if (!of_device_is_available(dn))
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return NULL;
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reg = of_get_property(dn, "reg", ®len);
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if (reg == NULL || reglen < 20)
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return NULL;
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devfn = (of_read_number(reg, 1) >> 8) & 0xff;
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/* Check if the PCI device is already there */
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dev = pci_get_slot(bus, devfn);
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if (dev) {
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pci_dev_put(dev);
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return dev;
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}
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/* Device removed permanently ? */
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#ifdef CONFIG_EEH
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if (edev && (edev->mode & EEH_DEV_REMOVED))
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return NULL;
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#endif
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/* create a new pci_dev for this device */
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dev = of_create_pci_dev(dn, bus, devfn);
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if (!dev)
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return NULL;
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pr_debug(" dev header type: %x\n", dev->hdr_type);
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return dev;
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}
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/**
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* __of_scan_bus - given a PCI bus node, setup bus and scan for child devices
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* @node: device tree node for the PCI bus
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* @bus: pci_bus structure for the PCI bus
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* @rescan_existing: Flag indicating bus has already been set up
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*/
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static void __of_scan_bus(struct device_node *node, struct pci_bus *bus,
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int rescan_existing)
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{
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struct device_node *child;
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struct pci_dev *dev;
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pr_debug("of_scan_bus(%pOF) bus no %d...\n",
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node, bus->number);
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/* Scan direct children */
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for_each_child_of_node(node, child) {
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dev = of_scan_pci_dev(bus, child);
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if (!dev)
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continue;
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pr_debug(" dev header type: %x\n", dev->hdr_type);
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}
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/* Apply all fixups necessary. We don't fixup the bus "self"
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* for an existing bridge that is being rescanned
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*/
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if (!rescan_existing)
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pcibios_setup_bus_self(bus);
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/* Now scan child busses */
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for_each_pci_bridge(dev, bus)
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of_scan_pci_bridge(dev);
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}
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/**
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* of_scan_bus - given a PCI bus node, setup bus and scan for child devices
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* @node: device tree node for the PCI bus
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* @bus: pci_bus structure for the PCI bus
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*/
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void of_scan_bus(struct device_node *node, struct pci_bus *bus)
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{
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__of_scan_bus(node, bus, 0);
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}
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EXPORT_SYMBOL_GPL(of_scan_bus);
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/**
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* of_rescan_bus - given a PCI bus node, scan for child devices
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* @node: device tree node for the PCI bus
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* @bus: pci_bus structure for the PCI bus
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*
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* Same as of_scan_bus, but for a pci_bus structure that has already been
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* setup.
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*/
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void of_rescan_bus(struct device_node *node, struct pci_bus *bus)
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{
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__of_scan_bus(node, bus, 1);
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}
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EXPORT_SYMBOL_GPL(of_rescan_bus);
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