mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
![Linus Torvalds](/assets/img/avatar_default.png)
dma-buf: - rename dma-buf-map to iosys-map core: - move buddy allocator to core - add pci/platform init macros - improve EDID parser deep color handling - EDID timing type 7 support - add GPD Win Max quirk - add yes/no helpers to string_helpers - flatten syncobj chains - add nomodeset support to lots of drivers - improve fb-helper clipping support - add default property value interface fbdev: - improve fbdev ops speed ttm: - add a backpointer from ttm bo->ttm resource dp: - move displayport headers - add a dp helper module bridge: - anx7625 atomic support, HDCP support panel: - split out panel-lvds and lvds bindings - find panels in OF subnodes privacy: - add chromeos privacy screen support fb: - hot unplug fw fb on forced removal simpledrm: - request region instead of marking ioresource busy - add panel oreintation property udmabuf: - fix oops with 0 pages amdgpu: - power management code cleanup - Enable freesync video mode by default - RAS code cleanup - Improve VRAM access for debug using SDMA - SR-IOV rework special register access and fixes - profiling power state request ioctl - expose IP discovery via sysfs - Cyan skillfish updates - GC 10.3.7, SDMA 5.2.7, DCN 3.1.6 updates - expose benchmark tests via debugfs - add module param to disable XGMI for testing - GPU reset debugfs register dumping support amdkfd: - CRIU support - SDMA queue fixes radeon: - UVD suspend fix - iMac backlight fix i915: - minimal parallel submission for execlists - DG2-G12 subplatform added - DG2 programming workarounds - DG2 accelerated migration support - flat CCS and CCS engine support for XeHP - initial small BAR support - drop fake LMEM support - ADL-N PCH support - bigjoiner updates - introduce VMA resources and async unbinding - register definitions cleanups - multi-FBC refactoring - DG1 OPROM over SPI support - ADL-N platform enabling - opregion mailbox #5 support - DP MST ESI improvements - drm device based logging - async flip optimisation for DG2 - CPU arch abstraction fixes - improve GuC ADS init to work on aarch64 - tweak TTM LRU priority hint - GuC 69.0.3 support - remove short term execbuf pins nouveau: - higher DP/eDP bitrates - backlight fixes msm: - dpu + dp support for sc8180x - dp support for sm8350 - dpu + dsi support for qcm2290 - 10nm dsi phy tuning support - bridge support for dp encoder - gpu support for additional 7c3 SKUs ingenic: - HDMI support for JZ4780 - aux channel EDID support ast: - AST2600 support - add wide screen support - create DP/DVI connectors omapdrm: - fix implicit dma_buf fencing vc4: - add CSC + full range support - better display firmware handoff panfrost: - add initial dual-core GPU support stm: - new revision support - fb handover support mediatek: - transfer display binding document to yaml format. - add mt8195 display device binding. - allow commands to be sent during video mode. - add wait_for_event for crtc disable by cmdq. tegra: - YUV format support rcar-du: - LVDS support for M3-W+ (R8A77961) exynos: - BGR pixel format for FIMD device -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmI71h4ACgkQDHTzWXnE hr6wKg//SvKFiEOhptua8Ao8XYkhXpg1/tgdAs4D7bZ0YgJyF4Im0RuFOKMmF3mN 0Y8AwguqrsmrOAFbK8B1WEysB66DmGlZN/V2Q75X7fui8xs4uGF2Fcxyr+265zhf vONPwAoxYr+KXqwOI1p1BP2QEL6bJTdu+nrXRsXIBIrWnw8ehXJlw3fDhgvG5QBn RPdbU7lQnd47hdYxkbe5SiZvWnPC46dJmpqsRJir0xjskR6juU36f34C4IKhTGwO NDPeWVgusVXtIC/F4X6RebCWG0f66h+CUFa9zeYIleI/2/5yZWXfcw6Obx8HgPkt gieiI0R4TpkVxeHCApCQ5UpxWgfSOXdoDoyw172bKQw7JCHVEkSwenyMEEwNet6r SCJrRmlB1PBI/iTWmhm9qgrU46ZZyAnQoTlCsXGzJncdP3hzGlA1embl00yfEl7f wzM35N20qd5T4VKUEF8QYF0fLZYmKw4cWVASu4hQ3qmGal6frilphz2J8JK8hQNq KhFqNbVTnZsQNr9LBCbrf0kOPaMzpmW+2vQG9ApdAb1N3gNPZT7ctti0Xq5N2OUR AipWFAsDPS2NPADKmBtDU55PgFH9MqUIsoHHXLV4Qi76dvCqYoN68qRQxrL7rpSu b0gr0YKU2QcIB/uytjOPHcgtI5Xvrh+q8JPz/dJ38/Esgjmk4wo= =uRsT -----END PGP SIGNATURE----- Merge tag 'drm-next-2022-03-24' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "Lots of work all over, Intel improving DG2 support, amdkfd CRIU support, msm new hw support, and faster fbdev support. dma-buf: - rename dma-buf-map to iosys-map core: - move buddy allocator to core - add pci/platform init macros - improve EDID parser deep color handling - EDID timing type 7 support - add GPD Win Max quirk - add yes/no helpers to string_helpers - flatten syncobj chains - add nomodeset support to lots of drivers - improve fb-helper clipping support - add default property value interface fbdev: - improve fbdev ops speed ttm: - add a backpointer from ttm bo->ttm resource dp: - move displayport headers - add a dp helper module bridge: - anx7625 atomic support, HDCP support panel: - split out panel-lvds and lvds bindings - find panels in OF subnodes privacy: - add chromeos privacy screen support fb: - hot unplug fw fb on forced removal simpledrm: - request region instead of marking ioresource busy - add panel oreintation property udmabuf: - fix oops with 0 pages amdgpu: - power management code cleanup - Enable freesync video mode by default - RAS code cleanup - Improve VRAM access for debug using SDMA - SR-IOV rework special register access and fixes - profiling power state request ioctl - expose IP discovery via sysfs - Cyan skillfish updates - GC 10.3.7, SDMA 5.2.7, DCN 3.1.6 updates - expose benchmark tests via debugfs - add module param to disable XGMI for testing - GPU reset debugfs register dumping support amdkfd: - CRIU support - SDMA queue fixes radeon: - UVD suspend fix - iMac backlight fix i915: - minimal parallel submission for execlists - DG2-G12 subplatform added - DG2 programming workarounds - DG2 accelerated migration support - flat CCS and CCS engine support for XeHP - initial small BAR support - drop fake LMEM support - ADL-N PCH support - bigjoiner updates - introduce VMA resources and async unbinding - register definitions cleanups - multi-FBC refactoring - DG1 OPROM over SPI support - ADL-N platform enabling - opregion mailbox #5 support - DP MST ESI improvements - drm device based logging - async flip optimisation for DG2 - CPU arch abstraction fixes - improve GuC ADS init to work on aarch64 - tweak TTM LRU priority hint - GuC 69.0.3 support - remove short term execbuf pins nouveau: - higher DP/eDP bitrates - backlight fixes msm: - dpu + dp support for sc8180x - dp support for sm8350 - dpu + dsi support for qcm2290 - 10nm dsi phy tuning support - bridge support for dp encoder - gpu support for additional 7c3 SKUs ingenic: - HDMI support for JZ4780 - aux channel EDID support ast: - AST2600 support - add wide screen support - create DP/DVI connectors omapdrm: - fix implicit dma_buf fencing vc4: - add CSC + full range support - better display firmware handoff panfrost: - add initial dual-core GPU support stm: - new revision support - fb handover support mediatek: - transfer display binding document to yaml format. - add mt8195 display device binding. - allow commands to be sent during video mode. - add wait_for_event for crtc disable by cmdq. tegra: - YUV format support rcar-du: - LVDS support for M3-W+ (R8A77961) exynos: - BGR pixel format for FIMD device" * tag 'drm-next-2022-03-24' of git://anongit.freedesktop.org/drm/drm: (1529 commits) drm/i915/display: Do not re-enable PSR after it was marked as not reliable drm/i915/display: Fix HPD short pulse handling for eDP drm/amdgpu: Use drm_mode_copy() drm/radeon: Use drm_mode_copy() drm/amdgpu: Use ternary operator in `vcn_v1_0_start()` drm/amdgpu: Remove pointless on stack mode copies drm/amd/pm: fix indenting in __smu_cmn_reg_print_error() drm/amdgpu/dc: fix typos in comments drm/amdgpu: fix typos in comments drm/amd/pm: fix typos in comments drm/amdgpu: Add stolen reserved memory for MI25 SRIOV. drm/amdgpu: Merge get_reserved_allocation to get_vbios_allocations. drm/amdkfd: evict svm bo worker handle error drm/amdgpu/vcn: fix vcn ring test failure in igt reload test drm/amdgpu: only allow secure submission on rings which support that drm/amdgpu: fixed the warnings reported by kernel test robot drm/amd/display: 3.2.177 drm/amd/display: [FW Promotion] Release 0.0.108.0 drm/amd/display: Add save/restore PANEL_PWRSEQ_REF_DIV2 drm/amd/display: Wait for hubp read line for Pollock ...
356 lines
9.6 KiB
C
356 lines
9.6 KiB
C
/**************************************************************************
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*
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* Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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/*
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* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
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*/
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#include <linux/cc_platform.h>
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#include <linux/export.h>
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#include <linux/highmem.h>
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#include <linux/ioport.h>
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#include <linux/iosys-map.h>
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#include <xen/xen.h>
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#include <drm/drm_cache.h>
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/* A small bounce buffer that fits on the stack. */
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#define MEMCPY_BOUNCE_SIZE 128
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#if defined(CONFIG_X86)
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#include <asm/smp.h>
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/*
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* clflushopt is an unordered instruction which needs fencing with mfence or
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* sfence to avoid ordering issues. For drm_clflush_page this fencing happens
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* in the caller.
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*/
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static void
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drm_clflush_page(struct page *page)
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{
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uint8_t *page_virtual;
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unsigned int i;
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const int size = boot_cpu_data.x86_clflush_size;
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if (unlikely(page == NULL))
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return;
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page_virtual = kmap_atomic(page);
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for (i = 0; i < PAGE_SIZE; i += size)
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clflushopt(page_virtual + i);
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kunmap_atomic(page_virtual);
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}
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static void drm_cache_flush_clflush(struct page *pages[],
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unsigned long num_pages)
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{
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unsigned long i;
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mb(); /*Full memory barrier used before so that CLFLUSH is ordered*/
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for (i = 0; i < num_pages; i++)
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drm_clflush_page(*pages++);
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mb(); /*Also used after CLFLUSH so that all cache is flushed*/
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}
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#endif
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/**
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* drm_clflush_pages - Flush dcache lines of a set of pages.
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* @pages: List of pages to be flushed.
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* @num_pages: Number of pages in the array.
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*
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* Flush every data cache line entry that points to an address belonging
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* to a page in the array.
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*/
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void
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drm_clflush_pages(struct page *pages[], unsigned long num_pages)
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{
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#if defined(CONFIG_X86)
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if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
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drm_cache_flush_clflush(pages, num_pages);
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return;
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}
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if (wbinvd_on_all_cpus())
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pr_err("Timed out waiting for cache flush\n");
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#elif defined(__powerpc__)
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unsigned long i;
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for (i = 0; i < num_pages; i++) {
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struct page *page = pages[i];
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void *page_virtual;
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if (unlikely(page == NULL))
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continue;
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page_virtual = kmap_atomic(page);
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flush_dcache_range((unsigned long)page_virtual,
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(unsigned long)page_virtual + PAGE_SIZE);
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kunmap_atomic(page_virtual);
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}
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#else
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WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
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#endif
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}
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EXPORT_SYMBOL(drm_clflush_pages);
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/**
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* drm_clflush_sg - Flush dcache lines pointing to a scather-gather.
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* @st: struct sg_table.
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*
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* Flush every data cache line entry that points to an address in the
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* sg.
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*/
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void
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drm_clflush_sg(struct sg_table *st)
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{
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#if defined(CONFIG_X86)
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if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
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struct sg_page_iter sg_iter;
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mb(); /*CLFLUSH is ordered only by using memory barriers*/
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for_each_sgtable_page(st, &sg_iter, 0)
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drm_clflush_page(sg_page_iter_page(&sg_iter));
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mb(); /*Make sure that all cache line entry is flushed*/
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return;
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}
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if (wbinvd_on_all_cpus())
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pr_err("Timed out waiting for cache flush\n");
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#else
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WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
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#endif
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}
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EXPORT_SYMBOL(drm_clflush_sg);
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/**
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* drm_clflush_virt_range - Flush dcache lines of a region
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* @addr: Initial kernel memory address.
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* @length: Region size.
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*
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* Flush every data cache line entry that points to an address in the
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* region requested.
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*/
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void
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drm_clflush_virt_range(void *addr, unsigned long length)
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{
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#if defined(CONFIG_X86)
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if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
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const int size = boot_cpu_data.x86_clflush_size;
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void *end = addr + length;
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addr = (void *)(((unsigned long)addr) & -size);
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mb(); /*CLFLUSH is only ordered with a full memory barrier*/
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for (; addr < end; addr += size)
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clflushopt(addr);
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clflushopt(end - 1); /* force serialisation */
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mb(); /*Ensure that every data cache line entry is flushed*/
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return;
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}
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if (wbinvd_on_all_cpus())
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pr_err("Timed out waiting for cache flush\n");
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#else
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WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
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#endif
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}
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EXPORT_SYMBOL(drm_clflush_virt_range);
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bool drm_need_swiotlb(int dma_bits)
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{
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struct resource *tmp;
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resource_size_t max_iomem = 0;
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/*
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* Xen paravirtual hosts require swiotlb regardless of requested dma
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* transfer size.
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*
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* NOTE: Really, what it requires is use of the dma_alloc_coherent
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* allocator used in ttm_dma_populate() instead of
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* ttm_populate_and_map_pages(), which bounce buffers so much in
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* Xen it leads to swiotlb buffer exhaustion.
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*/
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if (xen_pv_domain())
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return true;
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/*
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* Enforce dma_alloc_coherent when memory encryption is active as well
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* for the same reasons as for Xen paravirtual hosts.
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*/
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if (cc_platform_has(CC_ATTR_MEM_ENCRYPT))
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return true;
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for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling)
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max_iomem = max(max_iomem, tmp->end);
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return max_iomem > ((u64)1 << dma_bits);
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}
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EXPORT_SYMBOL(drm_need_swiotlb);
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static void memcpy_fallback(struct iosys_map *dst,
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const struct iosys_map *src,
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unsigned long len)
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{
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if (!dst->is_iomem && !src->is_iomem) {
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memcpy(dst->vaddr, src->vaddr, len);
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} else if (!src->is_iomem) {
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iosys_map_memcpy_to(dst, 0, src->vaddr, len);
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} else if (!dst->is_iomem) {
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memcpy_fromio(dst->vaddr, src->vaddr_iomem, len);
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} else {
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/*
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* Bounce size is not performance tuned, but using a
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* bounce buffer like this is significantly faster than
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* resorting to ioreadxx() + iowritexx().
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*/
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char bounce[MEMCPY_BOUNCE_SIZE];
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void __iomem *_src = src->vaddr_iomem;
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void __iomem *_dst = dst->vaddr_iomem;
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while (len >= MEMCPY_BOUNCE_SIZE) {
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memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE);
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memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE);
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_src += MEMCPY_BOUNCE_SIZE;
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_dst += MEMCPY_BOUNCE_SIZE;
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len -= MEMCPY_BOUNCE_SIZE;
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}
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if (len) {
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memcpy_fromio(bounce, _src, MEMCPY_BOUNCE_SIZE);
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memcpy_toio(_dst, bounce, MEMCPY_BOUNCE_SIZE);
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}
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}
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}
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#ifdef CONFIG_X86
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static DEFINE_STATIC_KEY_FALSE(has_movntdqa);
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static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len)
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{
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kernel_fpu_begin();
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while (len >= 4) {
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asm("movntdqa (%0), %%xmm0\n"
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"movntdqa 16(%0), %%xmm1\n"
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"movntdqa 32(%0), %%xmm2\n"
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"movntdqa 48(%0), %%xmm3\n"
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"movaps %%xmm0, (%1)\n"
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"movaps %%xmm1, 16(%1)\n"
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"movaps %%xmm2, 32(%1)\n"
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"movaps %%xmm3, 48(%1)\n"
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:: "r" (src), "r" (dst) : "memory");
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src += 64;
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dst += 64;
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len -= 4;
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}
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while (len--) {
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asm("movntdqa (%0), %%xmm0\n"
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"movaps %%xmm0, (%1)\n"
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:: "r" (src), "r" (dst) : "memory");
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src += 16;
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dst += 16;
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}
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kernel_fpu_end();
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}
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/*
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* __drm_memcpy_from_wc copies @len bytes from @src to @dst using
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* non-temporal instructions where available. Note that all arguments
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* (@src, @dst) must be aligned to 16 bytes and @len must be a multiple
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* of 16.
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*/
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static void __drm_memcpy_from_wc(void *dst, const void *src, unsigned long len)
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{
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if (unlikely(((unsigned long)dst | (unsigned long)src | len) & 15))
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memcpy(dst, src, len);
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else if (likely(len))
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__memcpy_ntdqa(dst, src, len >> 4);
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}
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/**
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* drm_memcpy_from_wc - Perform the fastest available memcpy from a source
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* that may be WC.
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* @dst: The destination pointer
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* @src: The source pointer
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* @len: The size of the area o transfer in bytes
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*
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* Tries an arch optimized memcpy for prefetching reading out of a WC region,
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* and if no such beast is available, falls back to a normal memcpy.
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*/
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void drm_memcpy_from_wc(struct iosys_map *dst,
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const struct iosys_map *src,
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unsigned long len)
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{
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if (WARN_ON(in_interrupt())) {
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memcpy_fallback(dst, src, len);
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return;
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}
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if (static_branch_likely(&has_movntdqa)) {
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__drm_memcpy_from_wc(dst->is_iomem ?
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(void __force *)dst->vaddr_iomem :
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dst->vaddr,
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src->is_iomem ?
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(void const __force *)src->vaddr_iomem :
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src->vaddr,
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len);
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return;
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}
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memcpy_fallback(dst, src, len);
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}
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EXPORT_SYMBOL(drm_memcpy_from_wc);
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/*
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* drm_memcpy_init_early - One time initialization of the WC memcpy code
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*/
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void drm_memcpy_init_early(void)
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{
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/*
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* Some hypervisors (e.g. KVM) don't support VEX-prefix instructions
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* emulation. So don't enable movntdqa in hypervisor guest.
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*/
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if (static_cpu_has(X86_FEATURE_XMM4_1) &&
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!boot_cpu_has(X86_FEATURE_HYPERVISOR))
|
|
static_branch_enable(&has_movntdqa);
|
|
}
|
|
#else
|
|
void drm_memcpy_from_wc(struct iosys_map *dst,
|
|
const struct iosys_map *src,
|
|
unsigned long len)
|
|
{
|
|
WARN_ON(in_interrupt());
|
|
|
|
memcpy_fallback(dst, src, len);
|
|
}
|
|
EXPORT_SYMBOL(drm_memcpy_from_wc);
|
|
|
|
void drm_memcpy_init_early(void)
|
|
{
|
|
}
|
|
#endif /* CONFIG_X86 */
|