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synced 2024-08-23 09:19:51 +00:00
![Jani Nikula](/assets/img/avatar_default.png)
Turns out many of the files that need i915_reg.h get it implicitly via {display/intel_de.h, gt/intel_context.h} -> i915_trace.h -> i915_irq.h -> i915_reg.h. Since i915_trace.h doesn't actually need i915_irq.h, makes sense to drop it, but that requires adding quite a few new includes all over the place. Prefer including i915_reg.h where needed instead of adding another implicit include, because eventually we'll want to split up i915_reg.h and only include the specific registers at each place. Also some places actually needed i915_irq.h too. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6e78a2e0ac1bffaf5af3b5ccc21dff05e6518cef.1668008071.git.jani.nikula@intel.com
432 lines
11 KiB
C
432 lines
11 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2018 Intel Corporation
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*/
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#include "i915_reg.h"
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#include "intel_combo_phy.h"
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#include "intel_combo_phy_regs.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#define for_each_combo_phy(__dev_priv, __phy) \
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for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
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for_each_if(intel_phy_is_combo(__dev_priv, __phy))
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#define for_each_combo_phy_reverse(__dev_priv, __phy) \
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for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
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for_each_if(intel_phy_is_combo(__dev_priv, __phy))
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enum {
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PROCMON_0_85V_DOT_0,
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PROCMON_0_95V_DOT_0,
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PROCMON_0_95V_DOT_1,
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PROCMON_1_05V_DOT_0,
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PROCMON_1_05V_DOT_1,
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};
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static const struct icl_procmon {
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const char *name;
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u32 dw1, dw9, dw10;
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} icl_procmon_values[] = {
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[PROCMON_0_85V_DOT_0] = {
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.name = "0.85V dot0 (low-voltage)",
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.dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96,
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},
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[PROCMON_0_95V_DOT_0] = {
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.name = "0.95V dot0",
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.dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB,
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},
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[PROCMON_0_95V_DOT_1] = {
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.name = "0.95V dot1",
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.dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5,
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},
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[PROCMON_1_05V_DOT_0] = {
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.name = "1.05V dot0",
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.dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1,
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},
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[PROCMON_1_05V_DOT_1] = {
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.name = "1.05V dot1",
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.dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1,
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},
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};
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static const struct icl_procmon *
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icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
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{
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u32 val;
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val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy));
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switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
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default:
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MISSING_CASE(val);
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fallthrough;
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case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
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return &icl_procmon_values[PROCMON_0_85V_DOT_0];
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case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0:
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return &icl_procmon_values[PROCMON_0_95V_DOT_0];
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case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1:
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return &icl_procmon_values[PROCMON_0_95V_DOT_1];
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case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0:
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return &icl_procmon_values[PROCMON_1_05V_DOT_0];
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case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1:
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return &icl_procmon_values[PROCMON_1_05V_DOT_1];
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}
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}
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static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
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enum phy phy)
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{
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const struct icl_procmon *procmon;
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u32 val;
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procmon = icl_get_procmon_ref_values(dev_priv, phy);
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val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));
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val &= ~((0xff << 16) | 0xff);
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val |= procmon->dw1;
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intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val);
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intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);
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intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);
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}
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static bool check_phy_reg(struct drm_i915_private *dev_priv,
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enum phy phy, i915_reg_t reg, u32 mask,
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u32 expected_val)
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{
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u32 val = intel_de_read(dev_priv, reg);
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if ((val & mask) != expected_val) {
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drm_dbg(&dev_priv->drm,
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"Combo PHY %c reg %08x state mismatch: "
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"current %08x mask %08x expected %08x\n",
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phy_name(phy),
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reg.reg, val, mask, expected_val);
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return false;
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}
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return true;
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}
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static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
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enum phy phy)
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{
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const struct icl_procmon *procmon;
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bool ret;
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procmon = icl_get_procmon_ref_values(dev_priv, phy);
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drm_dbg_kms(&dev_priv->drm,
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"Combo PHY %c Voltage/Process Info : %s\n",
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phy_name(phy), procmon->name);
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ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
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(0xff << 16) | 0xff, procmon->dw1);
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
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-1U, procmon->dw9);
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
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-1U, procmon->dw10);
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return ret;
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}
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static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
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{
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/*
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* Some platforms only expect PHY_MISC to be programmed for PHY-A and
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* PHY-B and may not even have instances of the register for the
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* other combo PHY's.
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*
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* ADL-S technically has three instances of PHY_MISC, but only requires
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* that we program it for PHY A.
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*/
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if (IS_ALDERLAKE_S(i915))
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return phy == PHY_A;
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else if (IS_JSL_EHL(i915) ||
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IS_ROCKETLAKE(i915) ||
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IS_DG1(i915))
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return phy < PHY_C;
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return true;
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}
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static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
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enum phy phy)
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{
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/* The PHY C added by EHL has no PHY_MISC register */
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if (!has_phy_misc(dev_priv, phy))
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return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
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else
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return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) &
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ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
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(intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
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}
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static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915)
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{
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bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A);
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bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D);
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bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
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/*
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* VBT's 'dvo port' field for child devices references the DDI, not
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* the PHY. So if combo PHY A is wired up to drive an external
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* display, we should see a child device present on PORT_D and
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* nothing on PORT_A and no DSI.
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*/
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if (ddi_d_present && !ddi_a_present && !dsi_present)
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return true;
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/*
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* If we encounter a VBT that claims to have an external display on
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* DDI-D _and_ an internal display on DDI-A/DSI leave an error message
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* in the log and let the internal display win.
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*/
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if (ddi_d_present)
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drm_err(&i915->drm,
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"VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n");
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return false;
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}
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static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
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{
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/*
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* Certain PHYs are connected to compensation resistors and act
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* as masters to other PHYs.
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*
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* ICL,TGL:
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* A(master) -> B(slave), C(slave)
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* RKL,DG1:
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* A(master) -> B(slave)
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* C(master) -> D(slave)
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* ADL-S:
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* A(master) -> B(slave), C(slave)
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* D(master) -> E(slave)
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*
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* We must set the IREFGEN bit for any PHY acting as a master
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* to another PHY.
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*/
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if (phy == PHY_A)
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return true;
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else if (IS_ALDERLAKE_S(dev_priv))
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return phy == PHY_D;
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else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
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return phy == PHY_C;
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return false;
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}
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static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
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enum phy phy)
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{
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bool ret = true;
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u32 expected_val = 0;
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if (!icl_combo_phy_enabled(dev_priv, phy))
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return false;
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if (DISPLAY_VER(dev_priv) >= 12) {
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy),
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ICL_PORT_TX_DW8_ODCC_CLK_SEL |
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ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
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ICL_PORT_TX_DW8_ODCC_CLK_SEL |
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ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
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DCC_MODE_SELECT_MASK,
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DCC_MODE_SELECT_CONTINUOSLY);
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}
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ret &= icl_verify_procmon_ref_values(dev_priv, phy);
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if (phy_is_master(dev_priv, phy)) {
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
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IREFGEN, IREFGEN);
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if (IS_JSL_EHL(dev_priv)) {
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if (ehl_vbt_ddi_d_present(dev_priv))
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expected_val = ICL_PHY_MISC_MUX_DDID;
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ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy),
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ICL_PHY_MISC_MUX_DDID,
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expected_val);
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}
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}
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
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CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
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return ret;
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}
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void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
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enum phy phy, bool is_dsi,
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int lane_count, bool lane_reversal)
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{
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u8 lane_mask;
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u32 val;
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if (is_dsi) {
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drm_WARN_ON(&dev_priv->drm, lane_reversal);
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switch (lane_count) {
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case 1:
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lane_mask = PWR_DOWN_LN_3_1_0;
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break;
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case 2:
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lane_mask = PWR_DOWN_LN_3_1;
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break;
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case 3:
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lane_mask = PWR_DOWN_LN_3;
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break;
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default:
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MISSING_CASE(lane_count);
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fallthrough;
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case 4:
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lane_mask = PWR_UP_ALL_LANES;
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break;
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}
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} else {
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switch (lane_count) {
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case 1:
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lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 :
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PWR_DOWN_LN_3_2_1;
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break;
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case 2:
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lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 :
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PWR_DOWN_LN_3_2;
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break;
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default:
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MISSING_CASE(lane_count);
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fallthrough;
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case 4:
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lane_mask = PWR_UP_ALL_LANES;
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break;
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}
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}
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val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy));
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val &= ~PWR_DOWN_LN_MASK;
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val |= lane_mask;
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intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
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}
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static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
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{
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enum phy phy;
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for_each_combo_phy(dev_priv, phy) {
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u32 val;
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if (icl_combo_phy_verify_state(dev_priv, phy)) {
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drm_dbg(&dev_priv->drm,
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"Combo PHY %c already enabled, won't reprogram it.\n",
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phy_name(phy));
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continue;
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}
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if (!has_phy_misc(dev_priv, phy))
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goto skip_phy_misc;
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/*
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* EHL's combo PHY A can be hooked up to either an external
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* display (via DDI-D) or an internal display (via DDI-A or
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* the DSI DPHY). This is a motherboard design decision that
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* can't be changed on the fly, so initialize the PHY's mux
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* based on whether our VBT indicates the presence of any
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* "internal" child devices.
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*/
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val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
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if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
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val &= ~ICL_PHY_MISC_MUX_DDID;
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if (ehl_vbt_ddi_d_present(dev_priv))
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val |= ICL_PHY_MISC_MUX_DDID;
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}
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val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
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intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
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skip_phy_misc:
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if (DISPLAY_VER(dev_priv) >= 12) {
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val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy));
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val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
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val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
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val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
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intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
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val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
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val &= ~DCC_MODE_SELECT_MASK;
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val |= DCC_MODE_SELECT_CONTINUOSLY;
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intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
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}
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icl_set_procmon_ref_values(dev_priv, phy);
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if (phy_is_master(dev_priv, phy)) {
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val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));
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val |= IREFGEN;
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intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);
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}
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val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));
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val |= COMP_INIT;
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intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);
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val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
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val |= CL_POWER_DOWN_ENABLE;
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intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
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}
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}
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static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
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{
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enum phy phy;
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for_each_combo_phy_reverse(dev_priv, phy) {
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u32 val;
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if (phy == PHY_A &&
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!icl_combo_phy_verify_state(dev_priv, phy)) {
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if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {
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/*
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* A known problem with old ifwi:
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* https://gitlab.freedesktop.org/drm/intel/-/issues/2411
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* Suppress the warning for CI. Remove ASAP!
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*/
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drm_dbg_kms(&dev_priv->drm,
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"Combo PHY %c HW state changed unexpectedly\n",
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phy_name(phy));
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} else {
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drm_warn(&dev_priv->drm,
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"Combo PHY %c HW state changed unexpectedly\n",
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phy_name(phy));
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}
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}
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if (!has_phy_misc(dev_priv, phy))
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goto skip_phy_misc;
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val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
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val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
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intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
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skip_phy_misc:
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val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));
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val &= ~COMP_INIT;
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intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);
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}
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}
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void intel_combo_phy_init(struct drm_i915_private *i915)
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{
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icl_combo_phys_init(i915);
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}
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void intel_combo_phy_uninit(struct drm_i915_private *i915)
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{
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icl_combo_phys_uninit(i915);
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}
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