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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
![Jani Nikula](/assets/img/avatar_default.png)
Turns out many of the files that need i915_reg.h get it implicitly via {display/intel_de.h, gt/intel_context.h} -> i915_trace.h -> i915_irq.h -> i915_reg.h. Since i915_trace.h doesn't actually need i915_irq.h, makes sense to drop it, but that requires adding quite a few new includes all over the place. Prefer including i915_reg.h where needed instead of adding another implicit include, because eventually we'll want to split up i915_reg.h and only include the specific registers at each place. Also some places actually needed i915_irq.h too. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6e78a2e0ac1bffaf5af3b5ccc21dff05e6518cef.1668008071.git.jani.nikula@intel.com
831 lines
23 KiB
C
831 lines
23 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#include <linux/kernel.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_atomic_uapi.h>
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#include <drm/drm_blend.h>
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#include <drm/drm_damage_helper.h>
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#include <drm/drm_fourcc.h>
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#include "i915_reg.h"
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#include "intel_atomic.h"
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#include "intel_atomic_plane.h"
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#include "intel_cursor.h"
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#include "intel_de.h"
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#include "intel_display.h"
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#include "intel_display_types.h"
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#include "intel_fb.h"
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#include "intel_fb_pin.h"
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#include "intel_frontbuffer.h"
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#include "intel_psr.h"
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#include "intel_sprite.h"
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#include "skl_watermark.h"
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/* Cursor formats */
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static const u32 intel_cursor_formats[] = {
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DRM_FORMAT_ARGB8888,
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};
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static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
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{
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struct drm_i915_private *dev_priv =
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to_i915(plane_state->uapi.plane->dev);
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const struct drm_framebuffer *fb = plane_state->hw.fb;
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const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
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u32 base;
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if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
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base = sg_dma_address(obj->mm.pages->sgl);
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else
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base = intel_plane_ggtt_offset(plane_state);
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return base + plane_state->view.color_plane[0].offset;
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}
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static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
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{
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int x = plane_state->uapi.dst.x1;
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int y = plane_state->uapi.dst.y1;
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u32 pos = 0;
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if (x < 0) {
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pos |= CURSOR_POS_X_SIGN;
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x = -x;
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}
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pos |= CURSOR_POS_X(x);
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if (y < 0) {
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pos |= CURSOR_POS_Y_SIGN;
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y = -y;
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}
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pos |= CURSOR_POS_Y(y);
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return pos;
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}
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static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
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{
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const struct drm_mode_config *config =
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&plane_state->uapi.plane->dev->mode_config;
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int width = drm_rect_width(&plane_state->uapi.dst);
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int height = drm_rect_height(&plane_state->uapi.dst);
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return width > 0 && width <= config->cursor_width &&
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height > 0 && height <= config->cursor_height;
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}
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static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
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{
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struct drm_i915_private *dev_priv =
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to_i915(plane_state->uapi.plane->dev);
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unsigned int rotation = plane_state->hw.rotation;
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int src_x, src_y;
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u32 offset;
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int ret;
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ret = intel_plane_compute_gtt(plane_state);
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if (ret)
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return ret;
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if (!plane_state->uapi.visible)
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return 0;
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src_x = plane_state->uapi.src.x1 >> 16;
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src_y = plane_state->uapi.src.y1 >> 16;
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intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
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offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
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plane_state, 0);
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if (src_x != 0 || src_y != 0) {
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drm_dbg_kms(&dev_priv->drm,
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"Arbitrary cursor panning not supported\n");
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return -EINVAL;
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}
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/*
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* Put the final coordinates back so that the src
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* coordinate checks will see the right values.
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*/
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drm_rect_translate_to(&plane_state->uapi.src,
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src_x << 16, src_y << 16);
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/* ILK+ do this automagically in hardware */
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if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
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const struct drm_framebuffer *fb = plane_state->hw.fb;
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int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
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int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
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offset += (src_h * src_w - 1) * fb->format->cpp[0];
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}
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plane_state->view.color_plane[0].offset = offset;
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plane_state->view.color_plane[0].x = src_x;
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plane_state->view.color_plane[0].y = src_y;
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return 0;
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}
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static int intel_check_cursor(struct intel_crtc_state *crtc_state,
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struct intel_plane_state *plane_state)
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{
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const struct drm_framebuffer *fb = plane_state->hw.fb;
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struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
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const struct drm_rect src = plane_state->uapi.src;
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const struct drm_rect dst = plane_state->uapi.dst;
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int ret;
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if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
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drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
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return -EINVAL;
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}
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ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
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DRM_PLANE_NO_SCALING,
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DRM_PLANE_NO_SCALING,
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true);
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if (ret)
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return ret;
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/* Use the unclipped src/dst rectangles, which we program to hw */
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plane_state->uapi.src = src;
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plane_state->uapi.dst = dst;
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/* final plane coordinates will be relative to the plane's pipe */
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drm_rect_translate(&plane_state->uapi.dst,
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-crtc_state->pipe_src.x1,
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-crtc_state->pipe_src.y1);
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ret = intel_cursor_check_surface(plane_state);
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if (ret)
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return ret;
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if (!plane_state->uapi.visible)
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return 0;
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ret = intel_plane_check_src_coordinates(plane_state);
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if (ret)
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return ret;
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return 0;
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}
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static unsigned int
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i845_cursor_max_stride(struct intel_plane *plane,
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u32 pixel_format, u64 modifier,
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unsigned int rotation)
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{
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return 2048;
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}
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static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
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{
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u32 cntl = 0;
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if (crtc_state->gamma_enable)
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cntl |= CURSOR_PIPE_GAMMA_ENABLE;
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return cntl;
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}
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static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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return CURSOR_ENABLE |
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CURSOR_FORMAT_ARGB |
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CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);
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}
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static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
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{
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int width = drm_rect_width(&plane_state->uapi.dst);
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/*
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* 845g/865g are only limited by the width of their cursors,
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* the height is arbitrary up to the precision of the register.
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*/
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return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
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}
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static int i845_check_cursor(struct intel_crtc_state *crtc_state,
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struct intel_plane_state *plane_state)
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{
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const struct drm_framebuffer *fb = plane_state->hw.fb;
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struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
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int ret;
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ret = intel_check_cursor(crtc_state, plane_state);
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if (ret)
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return ret;
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/* if we want to turn off the cursor ignore width and height */
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if (!fb)
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return 0;
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/* Check for which cursor types we support */
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if (!i845_cursor_size_ok(plane_state)) {
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drm_dbg_kms(&i915->drm,
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"Cursor dimension %dx%d not supported\n",
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drm_rect_width(&plane_state->uapi.dst),
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drm_rect_height(&plane_state->uapi.dst));
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return -EINVAL;
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}
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drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
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plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
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switch (fb->pitches[0]) {
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case 256:
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case 512:
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case 1024:
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case 2048:
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break;
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default:
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drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
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fb->pitches[0]);
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return -EINVAL;
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}
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plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
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return 0;
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}
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/* TODO: split into noarm+arm pair */
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static void i845_cursor_update_arm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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u32 cntl = 0, base = 0, pos = 0, size = 0;
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if (plane_state && plane_state->uapi.visible) {
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unsigned int width = drm_rect_width(&plane_state->uapi.dst);
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unsigned int height = drm_rect_height(&plane_state->uapi.dst);
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cntl = plane_state->ctl |
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i845_cursor_ctl_crtc(crtc_state);
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size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
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base = intel_cursor_base(plane_state);
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pos = intel_cursor_position(plane_state);
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}
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/* On these chipsets we can only modify the base/size/stride
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* whilst the cursor is disabled.
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*/
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if (plane->cursor.base != base ||
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plane->cursor.size != size ||
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plane->cursor.cntl != cntl) {
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intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
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intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
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intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
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intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
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intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
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plane->cursor.base = base;
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plane->cursor.size = size;
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plane->cursor.cntl = cntl;
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} else {
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intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
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}
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}
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static void i845_cursor_disable_arm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state)
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{
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i845_cursor_update_arm(plane, crtc_state, NULL);
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}
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static bool i845_cursor_get_hw_state(struct intel_plane *plane,
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enum pipe *pipe)
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{
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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enum intel_display_power_domain power_domain;
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intel_wakeref_t wakeref;
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bool ret;
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power_domain = POWER_DOMAIN_PIPE(PIPE_A);
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wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
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if (!wakeref)
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return false;
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ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
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*pipe = PIPE_A;
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intel_display_power_put(dev_priv, power_domain, wakeref);
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return ret;
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}
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static unsigned int
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i9xx_cursor_max_stride(struct intel_plane *plane,
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u32 pixel_format, u64 modifier,
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unsigned int rotation)
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{
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return plane->base.dev->mode_config.cursor_width * 4;
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}
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static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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u32 cntl = 0;
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if (DISPLAY_VER(dev_priv) >= 11)
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return cntl;
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if (crtc_state->gamma_enable)
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cntl = MCURSOR_PIPE_GAMMA_ENABLE;
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if (crtc_state->csc_enable)
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cntl |= MCURSOR_PIPE_CSC_ENABLE;
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if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
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cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
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return cntl;
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}
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static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state)
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{
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struct drm_i915_private *dev_priv =
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to_i915(plane_state->uapi.plane->dev);
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u32 cntl = 0;
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if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
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cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
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switch (drm_rect_width(&plane_state->uapi.dst)) {
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case 64:
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cntl |= MCURSOR_MODE_64_ARGB_AX;
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break;
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case 128:
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cntl |= MCURSOR_MODE_128_ARGB_AX;
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break;
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case 256:
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cntl |= MCURSOR_MODE_256_ARGB_AX;
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break;
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default:
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MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
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return 0;
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}
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if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
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cntl |= MCURSOR_ROTATE_180;
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/* Wa_22012358565:adl-p */
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if (DISPLAY_VER(dev_priv) == 13)
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cntl |= MCURSOR_ARB_SLOTS(1);
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return cntl;
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}
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static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
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{
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struct drm_i915_private *dev_priv =
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to_i915(plane_state->uapi.plane->dev);
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int width = drm_rect_width(&plane_state->uapi.dst);
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int height = drm_rect_height(&plane_state->uapi.dst);
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if (!intel_cursor_size_ok(plane_state))
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return false;
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/* Cursor width is limited to a few power-of-two sizes */
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switch (width) {
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case 256:
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case 128:
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case 64:
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break;
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default:
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return false;
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}
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/*
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* IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
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* height from 8 lines up to the cursor width, when the
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* cursor is not rotated. Everything else requires square
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* cursors.
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*/
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if (HAS_CUR_FBC(dev_priv) &&
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plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
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if (height < 8 || height > width)
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return false;
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} else {
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if (height != width)
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return false;
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}
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return true;
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}
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static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
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struct intel_plane_state *plane_state)
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{
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struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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const struct drm_framebuffer *fb = plane_state->hw.fb;
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enum pipe pipe = plane->pipe;
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int ret;
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ret = intel_check_cursor(crtc_state, plane_state);
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if (ret)
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return ret;
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/* if we want to turn off the cursor ignore width and height */
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if (!fb)
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return 0;
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/* Check for which cursor types we support */
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if (!i9xx_cursor_size_ok(plane_state)) {
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drm_dbg(&dev_priv->drm,
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"Cursor dimension %dx%d not supported\n",
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drm_rect_width(&plane_state->uapi.dst),
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drm_rect_height(&plane_state->uapi.dst));
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return -EINVAL;
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}
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drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
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plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
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if (fb->pitches[0] !=
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drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
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drm_dbg_kms(&dev_priv->drm,
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"Invalid cursor stride (%u) (cursor width %d)\n",
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fb->pitches[0],
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drm_rect_width(&plane_state->uapi.dst));
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return -EINVAL;
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}
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/*
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* There's something wrong with the cursor on CHV pipe C.
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* If it straddles the left edge of the screen then
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* moving it away from the edge or disabling it often
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* results in a pipe underrun, and often that can lead to
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* dead pipe (constant underrun reported, and it scans
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* out just a solid color). To recover from that, the
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* display power well must be turned off and on again.
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* Refuse the put the cursor into that compromised position.
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*/
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if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
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plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
"CHV cursor C not allowed to straddle the left screen edge\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* TODO: split into noarm+arm pair */
|
|
static void i9xx_cursor_update_arm(struct intel_plane *plane,
|
|
const struct intel_crtc_state *crtc_state,
|
|
const struct intel_plane_state *plane_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
|
enum pipe pipe = plane->pipe;
|
|
u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
|
|
|
|
if (plane_state && plane_state->uapi.visible) {
|
|
int width = drm_rect_width(&plane_state->uapi.dst);
|
|
int height = drm_rect_height(&plane_state->uapi.dst);
|
|
|
|
cntl = plane_state->ctl |
|
|
i9xx_cursor_ctl_crtc(crtc_state);
|
|
|
|
if (width != height)
|
|
fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
|
|
|
|
base = intel_cursor_base(plane_state);
|
|
pos = intel_cursor_position(plane_state);
|
|
}
|
|
|
|
/*
|
|
* On some platforms writing CURCNTR first will also
|
|
* cause CURPOS to be armed by the CURBASE write.
|
|
* Without the CURCNTR write the CURPOS write would
|
|
* arm itself. Thus we always update CURCNTR before
|
|
* CURPOS.
|
|
*
|
|
* On other platforms CURPOS always requires the
|
|
* CURBASE write to arm the update. Additonally
|
|
* a write to any of the cursor register will cancel
|
|
* an already armed cursor update. Thus leaving out
|
|
* the CURBASE write after CURPOS could lead to a
|
|
* cursor that doesn't appear to move, or even change
|
|
* shape. Thus we always write CURBASE.
|
|
*
|
|
* The other registers are armed by the CURBASE write
|
|
* except when the plane is getting enabled at which time
|
|
* the CURCNTR write arms the update.
|
|
*/
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 9)
|
|
skl_write_cursor_wm(plane, crtc_state);
|
|
|
|
if (plane_state)
|
|
intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
|
|
else
|
|
intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
|
|
|
|
if (plane->cursor.base != base ||
|
|
plane->cursor.size != fbc_ctl ||
|
|
plane->cursor.cntl != cntl) {
|
|
if (HAS_CUR_FBC(dev_priv))
|
|
intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
|
|
fbc_ctl);
|
|
intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
|
|
intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
|
|
intel_de_write_fw(dev_priv, CURBASE(pipe), base);
|
|
|
|
plane->cursor.base = base;
|
|
plane->cursor.size = fbc_ctl;
|
|
plane->cursor.cntl = cntl;
|
|
} else {
|
|
intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
|
|
intel_de_write_fw(dev_priv, CURBASE(pipe), base);
|
|
}
|
|
}
|
|
|
|
static void i9xx_cursor_disable_arm(struct intel_plane *plane,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
i9xx_cursor_update_arm(plane, crtc_state, NULL);
|
|
}
|
|
|
|
static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
|
|
enum pipe *pipe)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
|
enum intel_display_power_domain power_domain;
|
|
intel_wakeref_t wakeref;
|
|
bool ret;
|
|
u32 val;
|
|
|
|
/*
|
|
* Not 100% correct for planes that can move between pipes,
|
|
* but that's only the case for gen2-3 which don't have any
|
|
* display power wells.
|
|
*/
|
|
power_domain = POWER_DOMAIN_PIPE(plane->pipe);
|
|
wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
|
|
if (!wakeref)
|
|
return false;
|
|
|
|
val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
|
|
|
|
ret = val & MCURSOR_MODE_MASK;
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
|
|
*pipe = plane->pipe;
|
|
else
|
|
*pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
|
|
|
|
intel_display_power_put(dev_priv, power_domain, wakeref);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
|
|
u32 format, u64 modifier)
|
|
{
|
|
if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
|
|
return false;
|
|
|
|
return format == DRM_FORMAT_ARGB8888;
|
|
}
|
|
|
|
static int
|
|
intel_legacy_cursor_update(struct drm_plane *_plane,
|
|
struct drm_crtc *_crtc,
|
|
struct drm_framebuffer *fb,
|
|
int crtc_x, int crtc_y,
|
|
unsigned int crtc_w, unsigned int crtc_h,
|
|
u32 src_x, u32 src_y,
|
|
u32 src_w, u32 src_h,
|
|
struct drm_modeset_acquire_ctx *ctx)
|
|
{
|
|
struct intel_plane *plane = to_intel_plane(_plane);
|
|
struct intel_crtc *crtc = to_intel_crtc(_crtc);
|
|
struct intel_plane_state *old_plane_state =
|
|
to_intel_plane_state(plane->base.state);
|
|
struct intel_plane_state *new_plane_state;
|
|
struct intel_crtc_state *crtc_state =
|
|
to_intel_crtc_state(crtc->base.state);
|
|
struct intel_crtc_state *new_crtc_state;
|
|
int ret;
|
|
|
|
/*
|
|
* When crtc is inactive or there is a modeset pending,
|
|
* wait for it to complete in the slowpath.
|
|
* PSR2 selective fetch also requires the slow path as
|
|
* PSR2 plane and transcoder registers can only be updated during
|
|
* vblank.
|
|
*
|
|
* FIXME bigjoiner fastpath would be good
|
|
*/
|
|
if (!crtc_state->hw.active ||
|
|
intel_crtc_needs_modeset(crtc_state) ||
|
|
intel_crtc_needs_fastset(crtc_state) ||
|
|
crtc_state->bigjoiner_pipes)
|
|
goto slow;
|
|
|
|
/*
|
|
* Don't do an async update if there is an outstanding commit modifying
|
|
* the plane. This prevents our async update's changes from getting
|
|
* overridden by a previous synchronous update's state.
|
|
*/
|
|
if (old_plane_state->uapi.commit &&
|
|
!try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
|
|
goto slow;
|
|
|
|
/*
|
|
* If any parameters change that may affect watermarks,
|
|
* take the slowpath. Only changing fb or position should be
|
|
* in the fastpath.
|
|
*/
|
|
if (old_plane_state->uapi.crtc != &crtc->base ||
|
|
old_plane_state->uapi.src_w != src_w ||
|
|
old_plane_state->uapi.src_h != src_h ||
|
|
old_plane_state->uapi.crtc_w != crtc_w ||
|
|
old_plane_state->uapi.crtc_h != crtc_h ||
|
|
!old_plane_state->uapi.fb != !fb)
|
|
goto slow;
|
|
|
|
new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
|
|
if (!new_plane_state)
|
|
return -ENOMEM;
|
|
|
|
new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
|
|
if (!new_crtc_state) {
|
|
ret = -ENOMEM;
|
|
goto out_free;
|
|
}
|
|
|
|
drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
|
|
|
|
new_plane_state->uapi.src_x = src_x;
|
|
new_plane_state->uapi.src_y = src_y;
|
|
new_plane_state->uapi.src_w = src_w;
|
|
new_plane_state->uapi.src_h = src_h;
|
|
new_plane_state->uapi.crtc_x = crtc_x;
|
|
new_plane_state->uapi.crtc_y = crtc_y;
|
|
new_plane_state->uapi.crtc_w = crtc_w;
|
|
new_plane_state->uapi.crtc_h = crtc_h;
|
|
|
|
intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
|
|
|
|
ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
|
|
old_plane_state, new_plane_state);
|
|
if (ret)
|
|
goto out_free;
|
|
|
|
ret = intel_plane_pin_fb(new_plane_state);
|
|
if (ret)
|
|
goto out_free;
|
|
|
|
intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
|
|
ORIGIN_CURSOR_UPDATE);
|
|
intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
|
|
to_intel_frontbuffer(new_plane_state->hw.fb),
|
|
plane->frontbuffer_bit);
|
|
|
|
/* Swap plane state */
|
|
plane->base.state = &new_plane_state->uapi;
|
|
|
|
/*
|
|
* We cannot swap crtc_state as it may be in use by an atomic commit or
|
|
* page flip that's running simultaneously. If we swap crtc_state and
|
|
* destroy the old state, we will cause a use-after-free there.
|
|
*
|
|
* Only update active_planes, which is needed for our internal
|
|
* bookkeeping. Either value will do the right thing when updating
|
|
* planes atomically. If the cursor was part of the atomic update then
|
|
* we would have taken the slowpath.
|
|
*/
|
|
crtc_state->active_planes = new_crtc_state->active_planes;
|
|
|
|
/*
|
|
* Technically we should do a vblank evasion here to make
|
|
* sure all the cursor registers update on the same frame.
|
|
* For now just make sure the register writes happen as
|
|
* quickly as possible to minimize the race window.
|
|
*/
|
|
local_irq_disable();
|
|
|
|
if (new_plane_state->uapi.visible) {
|
|
intel_plane_update_noarm(plane, crtc_state, new_plane_state);
|
|
intel_plane_update_arm(plane, crtc_state, new_plane_state);
|
|
} else {
|
|
intel_plane_disable_arm(plane, crtc_state);
|
|
}
|
|
|
|
local_irq_enable();
|
|
|
|
intel_plane_unpin_fb(old_plane_state);
|
|
|
|
out_free:
|
|
if (new_crtc_state)
|
|
intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
|
|
if (ret)
|
|
intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
|
|
else
|
|
intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
|
|
return ret;
|
|
|
|
slow:
|
|
return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
|
|
crtc_x, crtc_y, crtc_w, crtc_h,
|
|
src_x, src_y, src_w, src_h, ctx);
|
|
}
|
|
|
|
static const struct drm_plane_funcs intel_cursor_plane_funcs = {
|
|
.update_plane = intel_legacy_cursor_update,
|
|
.disable_plane = drm_atomic_helper_disable_plane,
|
|
.destroy = intel_plane_destroy,
|
|
.atomic_duplicate_state = intel_plane_duplicate_state,
|
|
.atomic_destroy_state = intel_plane_destroy_state,
|
|
.format_mod_supported = intel_cursor_format_mod_supported,
|
|
};
|
|
|
|
struct intel_plane *
|
|
intel_cursor_plane_create(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe)
|
|
{
|
|
struct intel_plane *cursor;
|
|
int ret, zpos;
|
|
u64 *modifiers;
|
|
|
|
cursor = intel_plane_alloc();
|
|
if (IS_ERR(cursor))
|
|
return cursor;
|
|
|
|
cursor->pipe = pipe;
|
|
cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
|
|
cursor->id = PLANE_CURSOR;
|
|
cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
|
|
|
|
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
|
|
cursor->max_stride = i845_cursor_max_stride;
|
|
cursor->update_arm = i845_cursor_update_arm;
|
|
cursor->disable_arm = i845_cursor_disable_arm;
|
|
cursor->get_hw_state = i845_cursor_get_hw_state;
|
|
cursor->check_plane = i845_check_cursor;
|
|
} else {
|
|
cursor->max_stride = i9xx_cursor_max_stride;
|
|
cursor->update_arm = i9xx_cursor_update_arm;
|
|
cursor->disable_arm = i9xx_cursor_disable_arm;
|
|
cursor->get_hw_state = i9xx_cursor_get_hw_state;
|
|
cursor->check_plane = i9xx_check_cursor;
|
|
}
|
|
|
|
cursor->cursor.base = ~0;
|
|
cursor->cursor.cntl = ~0;
|
|
|
|
if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
|
|
cursor->cursor.size = ~0;
|
|
|
|
modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE);
|
|
|
|
ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
|
|
0, &intel_cursor_plane_funcs,
|
|
intel_cursor_formats,
|
|
ARRAY_SIZE(intel_cursor_formats),
|
|
modifiers,
|
|
DRM_PLANE_TYPE_CURSOR,
|
|
"cursor %c", pipe_name(pipe));
|
|
|
|
kfree(modifiers);
|
|
|
|
if (ret)
|
|
goto fail;
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 4)
|
|
drm_plane_create_rotation_property(&cursor->base,
|
|
DRM_MODE_ROTATE_0,
|
|
DRM_MODE_ROTATE_0 |
|
|
DRM_MODE_ROTATE_180);
|
|
|
|
zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
|
|
drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 12)
|
|
drm_plane_enable_fb_damage_clips(&cursor->base);
|
|
|
|
intel_plane_helper_add(cursor);
|
|
|
|
return cursor;
|
|
|
|
fail:
|
|
intel_plane_free(cursor);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|