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![Jani Nikula](/assets/img/avatar_default.png)
Move display suspend/resume and display reset modeset state and ctx members under drm_i915_private display sub-struct. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221109144209.3624739-4-jani.nikula@intel.com
452 lines
10 KiB
C
452 lines
10 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_DISPLAY_CORE_H__
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#define __INTEL_DISPLAY_CORE_H__
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#include <linux/list.h>
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#include <linux/llist.h>
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#include <linux/mutex.h>
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#include <linux/types.h>
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#include <linux/wait.h>
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#include <linux/workqueue.h>
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#include <drm/drm_connector.h>
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#include <drm/drm_modeset_lock.h>
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#include "intel_cdclk.h"
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#include "intel_display.h"
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#include "intel_display_power.h"
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#include "intel_dmc.h"
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#include "intel_dpll_mgr.h"
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#include "intel_fbc.h"
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#include "intel_global_state.h"
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#include "intel_gmbus.h"
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#include "intel_opregion.h"
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#include "intel_pm_types.h"
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struct drm_i915_private;
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struct drm_property;
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struct drm_property_blob;
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struct i915_audio_component;
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struct i915_hdcp_comp_master;
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struct intel_atomic_state;
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struct intel_audio_funcs;
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struct intel_bios_encoder_data;
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struct intel_cdclk_funcs;
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struct intel_cdclk_vals;
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struct intel_color_funcs;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_dpll_funcs;
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struct intel_dpll_mgr;
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struct intel_fbdev;
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struct intel_fdi_funcs;
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struct intel_hotplug_funcs;
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struct intel_initial_plane_config;
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struct intel_overlay;
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/* Amount of SAGV/QGV points, BSpec precisely defines this */
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#define I915_NUM_QGV_POINTS 8
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/* Amount of PSF GV points, BSpec precisely defines this */
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#define I915_NUM_PSF_GV_POINTS 3
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struct intel_display_funcs {
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/*
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* Returns the active state of the crtc, and if the crtc is active,
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* fills out the pipe-config with the hw state.
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*/
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bool (*get_pipe_config)(struct intel_crtc *,
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struct intel_crtc_state *);
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void (*get_initial_plane_config)(struct intel_crtc *,
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struct intel_initial_plane_config *);
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void (*crtc_enable)(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void (*crtc_disable)(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void (*commit_modeset_enables)(struct intel_atomic_state *state);
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};
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/* functions used for watermark calcs for display. */
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struct intel_wm_funcs {
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/* update_wm is for legacy wm management */
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void (*update_wm)(struct drm_i915_private *dev_priv);
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int (*compute_pipe_wm)(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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int (*compute_intermediate_wm)(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void (*initial_watermarks)(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void (*atomic_update_watermarks)(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void (*optimize_watermarks)(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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int (*compute_global_watermarks)(struct intel_atomic_state *state);
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};
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struct intel_audio {
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/* hda/i915 audio component */
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struct i915_audio_component *component;
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bool component_registered;
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/* mutex for audio/video sync */
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struct mutex mutex;
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int power_refcount;
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u32 freq_cntrl;
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/* Used to save the pipe-to-encoder mapping for audio */
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struct intel_encoder *encoder_map[I915_MAX_PIPES];
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/* necessary resource sharing with HDMI LPE audio driver. */
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struct {
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struct platform_device *platdev;
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int irq;
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} lpe;
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};
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/*
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* dpll and cdclk state is protected by connection_mutex dpll.lock serializes
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* intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
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* dpll, because on some platforms plls share registers.
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*/
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struct intel_dpll {
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struct mutex lock;
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int num_shared_dpll;
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struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
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const struct intel_dpll_mgr *mgr;
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struct {
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int nssc;
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int ssc;
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} ref_clks;
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};
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struct intel_frontbuffer_tracking {
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spinlock_t lock;
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/*
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* Tracking bits for delayed frontbuffer flushing du to gpu activity or
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* scheduled flips.
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*/
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unsigned busy_bits;
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unsigned flip_bits;
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};
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struct intel_hotplug {
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struct delayed_work hotplug_work;
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const u32 *hpd, *pch_hpd;
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struct {
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unsigned long last_jiffies;
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int count;
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enum {
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HPD_ENABLED = 0,
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HPD_DISABLED = 1,
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HPD_MARK_DISABLED = 2
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} state;
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} stats[HPD_NUM_PINS];
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u32 event_bits;
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u32 retry_bits;
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struct delayed_work reenable_work;
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u32 long_port_mask;
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u32 short_port_mask;
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struct work_struct dig_port_work;
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struct work_struct poll_init_work;
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bool poll_enabled;
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unsigned int hpd_storm_threshold;
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/* Whether or not to count short HPD IRQs in HPD storms */
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u8 hpd_short_storm_enabled;
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/*
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* if we get a HPD irq from DP and a HPD irq from non-DP
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* the non-DP HPD could block the workqueue on a mode config
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* mutex getting, that userspace may have taken. However
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* userspace is waiting on the DP workqueue to run which is
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* blocked behind the non-DP one.
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*/
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struct workqueue_struct *dp_wq;
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};
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struct intel_vbt_data {
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/* bdb version */
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u16 version;
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/* Feature bits */
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unsigned int int_tv_support:1;
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unsigned int int_crt_support:1;
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unsigned int lvds_use_ssc:1;
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unsigned int int_lvds_support:1;
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unsigned int display_clock_mode:1;
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unsigned int fdi_rx_polarity_inverted:1;
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int lvds_ssc_freq;
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enum drm_panel_orientation orientation;
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bool override_afc_startup;
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u8 override_afc_startup_val;
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int crt_ddc_pin;
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struct list_head display_devices;
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struct list_head bdb_blocks;
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struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */
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struct sdvo_device_mapping {
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u8 initialized;
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u8 dvo_port;
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u8 slave_addr;
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u8 dvo_wiring;
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u8 i2c_pin;
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u8 ddc_pin;
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} sdvo_mappings[2];
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};
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struct intel_wm {
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/*
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* Raw watermark latency values:
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* in 0.1us units for WM0,
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* in 0.5us units for WM1+.
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*/
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/* primary */
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u16 pri_latency[5];
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/* sprite */
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u16 spr_latency[5];
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/* cursor */
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u16 cur_latency[5];
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/*
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* Raw watermark memory latency values
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* for SKL for all 8 levels
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* in 1us units.
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*/
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u16 skl_latency[8];
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/* current hardware state */
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union {
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struct ilk_wm_values hw;
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struct vlv_wm_values vlv;
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struct g4x_wm_values g4x;
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};
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u8 max_level;
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/*
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* Should be held around atomic WM register writing; also
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* protects * intel_crtc->wm.active and
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* crtc_state->wm.need_postvbl_update.
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*/
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struct mutex wm_mutex;
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bool ipc_enabled;
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};
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struct intel_display {
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/* Display functions */
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struct {
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/* Top level crtc-ish functions */
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const struct intel_display_funcs *display;
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/* Display CDCLK functions */
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const struct intel_cdclk_funcs *cdclk;
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/* Display pll funcs */
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const struct intel_dpll_funcs *dpll;
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/* irq display functions */
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const struct intel_hotplug_funcs *hotplug;
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/* pm display functions */
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const struct intel_wm_funcs *wm;
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/* fdi display functions */
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const struct intel_fdi_funcs *fdi;
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/* Display internal color functions */
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const struct intel_color_funcs *color;
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/* Display internal audio functions */
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const struct intel_audio_funcs *audio;
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} funcs;
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/* Grouping using anonymous structs. Keep sorted. */
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struct intel_atomic_helper {
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struct llist_head free_list;
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struct work_struct free_work;
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} atomic_helper;
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struct {
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/* backlight registers and fields in struct intel_panel */
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struct mutex lock;
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} backlight;
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struct {
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struct intel_global_obj obj;
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struct intel_bw_info {
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/* for each QGV point */
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unsigned int deratedbw[I915_NUM_QGV_POINTS];
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/* for each PSF GV point */
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unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
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u8 num_qgv_points;
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u8 num_psf_gv_points;
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u8 num_planes;
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} max[6];
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} bw;
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struct {
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/* The current hardware cdclk configuration */
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struct intel_cdclk_config hw;
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/* cdclk, divider, and ratio table from bspec */
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const struct intel_cdclk_vals *table;
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struct intel_global_obj obj;
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unsigned int max_cdclk_freq;
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} cdclk;
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struct {
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struct drm_property_blob *glk_linear_degamma_lut;
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} color;
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struct {
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/* The current hardware dbuf configuration */
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u8 enabled_slices;
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struct intel_global_obj obj;
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} dbuf;
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struct {
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/*
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* dkl.phy_lock protects against concurrent access of the
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* Dekel TypeC PHYs.
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*/
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spinlock_t phy_lock;
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} dkl;
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struct {
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/* VLV/CHV/BXT/GLK DSI MMIO register base address */
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u32 mmio_base;
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} dsi;
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struct {
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/* list of fbdev register on this device */
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struct intel_fbdev *fbdev;
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struct work_struct suspend_work;
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} fbdev;
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struct {
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unsigned int pll_freq;
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u32 rx_config;
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} fdi;
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struct {
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struct list_head obj_list;
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} global;
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struct {
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/*
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* Base address of where the gmbus and gpio blocks are located
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* (either on PCH or on SoC for platforms without PCH).
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*/
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u32 mmio_base;
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/*
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* gmbus.mutex protects against concurrent usage of the single
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* hw gmbus controller on different i2c buses.
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*/
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struct mutex mutex;
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struct intel_gmbus *bus[GMBUS_NUM_PINS];
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wait_queue_head_t wait_queue;
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} gmbus;
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struct {
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struct i915_hdcp_comp_master *master;
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bool comp_added;
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/* Mutex to protect the above hdcp component related values. */
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struct mutex comp_mutex;
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} hdcp;
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struct {
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/*
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* HTI (aka HDPORT) state read during initial hw readout. Most
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* platforms don't have HTI, so this will just stay 0. Those
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* that do will use this later to figure out which PLLs and PHYs
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* are unavailable for driver usage.
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*/
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u32 state;
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} hti;
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struct {
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struct i915_power_domains domains;
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/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
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u32 chv_phy_control;
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/* perform PHY state sanity checks? */
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bool chv_phy_assert[2];
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} power;
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struct {
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u32 mmio_base;
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/* protects panel power sequencer state */
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struct mutex mutex;
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} pps;
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struct {
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struct drm_property *broadcast_rgb;
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struct drm_property *force_audio;
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} properties;
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struct {
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unsigned long mask;
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} quirks;
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struct {
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/* restore state for suspend/resume and display reset */
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struct drm_atomic_state *modeset_state;
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struct drm_modeset_acquire_ctx reset_ctx;
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} restore;
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struct {
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enum {
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I915_SAGV_UNKNOWN = 0,
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I915_SAGV_DISABLED,
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I915_SAGV_ENABLED,
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I915_SAGV_NOT_CONTROLLED
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} status;
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u32 block_time_us;
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} sagv;
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struct {
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/* ordered wq for modesets */
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struct workqueue_struct *modeset;
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/* unbound hipri wq for page flips/plane updates */
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struct workqueue_struct *flip;
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} wq;
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/* Grouping using named structs. Keep sorted. */
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struct intel_audio audio;
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struct intel_dmc dmc;
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struct intel_dpll dpll;
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struct intel_fbc *fbc[I915_MAX_FBCS];
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struct intel_frontbuffer_tracking fb_tracking;
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struct intel_hotplug hotplug;
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struct intel_opregion opregion;
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struct intel_overlay *overlay;
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struct intel_vbt_data vbt;
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struct intel_wm wm;
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};
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#endif /* __INTEL_DISPLAY_CORE_H__ */
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