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b8ed55335e
Not all Dekel PHY registers have a lane instance, so having to specify this when using them is awkward. It makes more sense to define each PHY register with its full internal PHY offset where bits 15:12 is the lane for lane-instanced PHY registers and just a register bank index for other PHY registers. This way lane-instanced registers can be referred to with the (tc_port, lane) parameters, while other registers just with a tc_port parameter. An additional benefit of this change is to prevent passing a Dekel register to a generic MMIO access function or vice versa. v2: - Fix parameter reuse in the DKL_REG_MMIO definition. v3: - Rebase on latest patchset version. Cc: Jani Nikula <jani.nikula@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221025114457.2191004-3-imre.deak@intel.com
106 lines
2.5 KiB
C
106 lines
2.5 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_de.h"
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#include "intel_display.h"
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#include "intel_dkl_phy.h"
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#include "intel_dkl_phy_regs.h"
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static void
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dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
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{
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enum tc_port tc_port = DKL_REG_TC_PORT(reg);
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drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
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intel_de_write(i915,
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HIP_INDEX_REG(tc_port),
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HIP_INDEX_VAL(tc_port, reg.bank_idx));
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}
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/**
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* intel_dkl_phy_read - read a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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*
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* Read the @reg Dekel PHY register.
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*
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* Returns the read value.
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*/
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u32
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intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
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{
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u32 val;
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg);
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val = intel_de_read(i915, DKL_REG_MMIO(reg));
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spin_unlock(&i915->display.dkl.phy_lock);
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return val;
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}
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/**
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* intel_dkl_phy_write - write a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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* @val: value to write
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*
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* Write @val to the @reg Dekel PHY register.
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*/
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void
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intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val)
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{
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg);
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intel_de_write(i915, DKL_REG_MMIO(reg), val);
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spin_unlock(&i915->display.dkl.phy_lock);
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}
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/**
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* intel_dkl_phy_rmw - read-modify-write a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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* @clear: mask to clear
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* @set: mask to set
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*
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* Read the @reg Dekel PHY register, clearing then setting the @clear/@set bits in it, and writing
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* this value back to the register if the value differs from the read one.
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*/
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void
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intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
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{
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg);
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intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set);
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spin_unlock(&i915->display.dkl.phy_lock);
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}
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/**
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* intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register
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* @i915: i915 device instance
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* @reg: Dekel PHY register
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*
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* Read the @reg Dekel PHY register without returning the read value.
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*/
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void
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intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
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{
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spin_lock(&i915->display.dkl.phy_lock);
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dkl_phy_set_hip_idx(i915, reg);
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intel_de_posting_read(i915, DKL_REG_MMIO(reg));
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spin_unlock(&i915->display.dkl.phy_lock);
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}
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