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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
![Ville Syrjälä](/assets/img/avatar_default.png)
Move the panel specific VBT parsing to happen during the output probing stage. Needs to be done because the VBT parsing will need to look at the EDID to determine the correct panel_type on some machines. We split the parsed VBT data (i915->vbt) along the same boundary. For the moment we just hoist all the panel specific stuff into connector->panel.vbt since that seems like the most convenient place for eg. the backlight code. Note that we simply drop the drrs type check from intel_drrs_frontbuffer_update() since that operates on the whole device rather than a specific connector/encoder. But the check was just a micro optimization so removing it doesn't actually mattter for correctness. TODO: Lot's of cleanup to be done in the future. Eg. most of the DSI stuff could probably be eliminated entirely and just parsed on demand during DSI init. v2: Note the intel_drrs_frontbuffer_update() change Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-13-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
960 lines
28 KiB
C
960 lines
28 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Author: Shobhit Kumar <shobhit.kumar@intel.com>
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*
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*/
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#include <linux/gpio/consumer.h>
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#include <linux/gpio/machine.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/slab.h>
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#include <linux/string_helpers.h>
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#include <asm/unaligned.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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#include <video/mipi_display.h>
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_display_types.h"
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#include "intel_dsi.h"
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#include "intel_dsi_vbt.h"
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#include "vlv_dsi.h"
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#include "vlv_dsi_regs.h"
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#include "vlv_sideband.h"
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#define MIPI_TRANSFER_MODE_SHIFT 0
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#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
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#define MIPI_PORT_SHIFT 3
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/* base offsets for gpio pads */
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#define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130
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#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
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#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
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#define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140
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#define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150
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#define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160
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#define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180
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#define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190
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#define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170
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#define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100
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#define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0
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#define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0
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#define VLV_GPIO_PCONF0(base_offset) (base_offset)
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#define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8)
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struct gpio_map {
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u16 base_offset;
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bool init;
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};
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static struct gpio_map vlv_gpio_table[] = {
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{ VLV_GPIO_NC_0_HV_DDI0_HPD },
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{ VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
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{ VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
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{ VLV_GPIO_NC_3_PANEL0_VDDEN },
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{ VLV_GPIO_NC_4_PANEL0_BKLTEN },
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{ VLV_GPIO_NC_5_PANEL0_BKLTCTL },
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{ VLV_GPIO_NC_6_HV_DDI1_HPD },
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{ VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
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{ VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
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{ VLV_GPIO_NC_9_PANEL1_VDDEN },
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{ VLV_GPIO_NC_10_PANEL1_BKLTEN },
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{ VLV_GPIO_NC_11_PANEL1_BKLTCTL },
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};
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struct i2c_adapter_lookup {
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u16 slave_addr;
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struct intel_dsi *intel_dsi;
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acpi_handle dev_handle;
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};
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#define CHV_GPIO_IDX_START_N 0
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#define CHV_GPIO_IDX_START_E 73
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#define CHV_GPIO_IDX_START_SW 100
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#define CHV_GPIO_IDX_START_SE 198
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#define CHV_VBT_MAX_PINS_PER_FMLY 15
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#define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8)
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#define CHV_GPIO_GPIOEN (1 << 15)
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#define CHV_GPIO_GPIOCFG_GPIO (0 << 8)
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#define CHV_GPIO_GPIOCFG_GPO (1 << 8)
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#define CHV_GPIO_GPIOCFG_GPI (2 << 8)
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#define CHV_GPIO_GPIOCFG_HIZ (3 << 8)
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#define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1)
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#define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
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#define CHV_GPIO_CFGLOCK (1 << 31)
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/* ICL DSI Display GPIO Pins */
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#define ICL_GPIO_DDSP_HPD_A 0
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#define ICL_GPIO_L_VDDEN_1 1
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#define ICL_GPIO_L_BKLTEN_1 2
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#define ICL_GPIO_DDPA_CTRLCLK_1 3
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#define ICL_GPIO_DDPA_CTRLDATA_1 4
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#define ICL_GPIO_DDSP_HPD_B 5
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#define ICL_GPIO_L_VDDEN_2 6
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#define ICL_GPIO_L_BKLTEN_2 7
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#define ICL_GPIO_DDPA_CTRLCLK_2 8
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#define ICL_GPIO_DDPA_CTRLDATA_2 9
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static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,
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u8 seq_port)
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{
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/*
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* If single link DSI is being used on any port, the VBT sequence block
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* send packet apparently always has 0 for the port. Just use the port
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* we have configured, and ignore the sequence block port.
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*/
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if (hweight8(intel_dsi->ports) == 1)
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return ffs(intel_dsi->ports) - 1;
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if (seq_port) {
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if (intel_dsi->ports & PORT_B)
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return PORT_B;
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else if (intel_dsi->ports & PORT_C)
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return PORT_C;
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}
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return PORT_A;
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}
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static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
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const u8 *data)
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{
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struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
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struct mipi_dsi_device *dsi_device;
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u8 type, flags, seq_port;
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u16 len;
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enum port port;
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drm_dbg_kms(&dev_priv->drm, "\n");
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flags = *data++;
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type = *data++;
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len = *((u16 *) data);
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data += 2;
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seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
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port = intel_dsi_seq_port_to_port(intel_dsi, seq_port);
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if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port]))
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goto out;
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dsi_device = intel_dsi->dsi_hosts[port]->device;
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if (!dsi_device) {
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drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",
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port_name(port));
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goto out;
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}
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if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
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dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
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else
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dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
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dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
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switch (type) {
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case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
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mipi_dsi_generic_write(dsi_device, NULL, 0);
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
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mipi_dsi_generic_write(dsi_device, data, 1);
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
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mipi_dsi_generic_write(dsi_device, data, 2);
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break;
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case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
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drm_dbg(&dev_priv->drm,
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"Generic Read not yet implemented or used\n");
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break;
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case MIPI_DSI_GENERIC_LONG_WRITE:
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mipi_dsi_generic_write(dsi_device, data, len);
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break;
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case MIPI_DSI_DCS_SHORT_WRITE:
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mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
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break;
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
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break;
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case MIPI_DSI_DCS_READ:
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drm_dbg(&dev_priv->drm,
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"DCS Read not yet implemented or used\n");
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break;
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case MIPI_DSI_DCS_LONG_WRITE:
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mipi_dsi_dcs_write_buffer(dsi_device, data, len);
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break;
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}
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if (DISPLAY_VER(dev_priv) < 11)
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vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
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out:
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data += len;
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return data;
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}
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static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
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{
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struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
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u32 delay = *((const u32 *) data);
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drm_dbg_kms(&i915->drm, "\n");
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usleep_range(delay, delay + 10);
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data += 4;
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return data;
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}
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static void vlv_exec_gpio(struct intel_connector *connector,
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u8 gpio_source, u8 gpio_index, bool value)
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{
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struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
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struct gpio_map *map;
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u16 pconf0, padval;
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u32 tmp;
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u8 port;
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if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
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drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n",
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gpio_index);
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return;
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}
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map = &vlv_gpio_table[gpio_index];
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if (connector->panel.vbt.dsi.seq_version >= 3) {
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/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
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port = IOSF_PORT_GPIO_NC;
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} else {
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if (gpio_source == 0) {
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port = IOSF_PORT_GPIO_NC;
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} else if (gpio_source == 1) {
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drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n");
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return;
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} else {
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drm_dbg_kms(&dev_priv->drm,
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"unknown gpio source %u\n", gpio_source);
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return;
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}
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}
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pconf0 = VLV_GPIO_PCONF0(map->base_offset);
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padval = VLV_GPIO_PAD_VAL(map->base_offset);
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vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
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if (!map->init) {
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/* FIXME: remove constant below */
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vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
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map->init = true;
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}
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tmp = 0x4 | value;
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vlv_iosf_sb_write(dev_priv, port, padval, tmp);
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vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
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}
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static void chv_exec_gpio(struct intel_connector *connector,
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u8 gpio_source, u8 gpio_index, bool value)
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{
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struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
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u16 cfg0, cfg1;
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u16 family_num;
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u8 port;
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if (connector->panel.vbt.dsi.seq_version >= 3) {
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if (gpio_index >= CHV_GPIO_IDX_START_SE) {
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/* XXX: it's unclear whether 255->57 is part of SE. */
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gpio_index -= CHV_GPIO_IDX_START_SE;
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port = CHV_IOSF_PORT_GPIO_SE;
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} else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
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gpio_index -= CHV_GPIO_IDX_START_SW;
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port = CHV_IOSF_PORT_GPIO_SW;
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} else if (gpio_index >= CHV_GPIO_IDX_START_E) {
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gpio_index -= CHV_GPIO_IDX_START_E;
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port = CHV_IOSF_PORT_GPIO_E;
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} else {
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port = CHV_IOSF_PORT_GPIO_N;
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}
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} else {
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/* XXX: The spec is unclear about CHV GPIO on seq v2 */
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if (gpio_source != 0) {
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drm_dbg_kms(&dev_priv->drm,
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"unknown gpio source %u\n", gpio_source);
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return;
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}
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if (gpio_index >= CHV_GPIO_IDX_START_E) {
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drm_dbg_kms(&dev_priv->drm,
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"invalid gpio index %u for GPIO N\n",
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gpio_index);
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return;
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}
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port = CHV_IOSF_PORT_GPIO_N;
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}
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family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
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gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
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cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
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cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
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vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
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vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
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vlv_iosf_sb_write(dev_priv, port, cfg0,
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CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
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CHV_GPIO_GPIOTXSTATE(value));
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vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
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}
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static void bxt_exec_gpio(struct intel_connector *connector,
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u8 gpio_source, u8 gpio_index, bool value)
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{
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struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
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/* XXX: this table is a quick ugly hack. */
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static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
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struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
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if (!gpio_desc) {
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gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
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NULL, gpio_index,
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value ? GPIOD_OUT_LOW :
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GPIOD_OUT_HIGH);
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if (IS_ERR_OR_NULL(gpio_desc)) {
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drm_err(&dev_priv->drm,
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"GPIO index %u request failed (%ld)\n",
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gpio_index, PTR_ERR(gpio_desc));
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return;
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}
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bxt_gpio_table[gpio_index] = gpio_desc;
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}
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gpiod_set_value(gpio_desc, value);
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}
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static void icl_exec_gpio(struct intel_connector *connector,
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u8 gpio_source, u8 gpio_index, bool value)
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{
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struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
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drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n");
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}
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static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
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{
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struct drm_device *dev = intel_dsi->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_connector *connector = intel_dsi->attached_connector;
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u8 gpio_source, gpio_index = 0, gpio_number;
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bool value;
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drm_dbg_kms(&dev_priv->drm, "\n");
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if (connector->panel.vbt.dsi.seq_version >= 3)
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gpio_index = *data++;
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gpio_number = *data++;
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/* gpio source in sequence v2 only */
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if (connector->panel.vbt.dsi.seq_version == 2)
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gpio_source = (*data >> 1) & 3;
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else
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gpio_source = 0;
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/* pull up/down */
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value = *data++ & 1;
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if (DISPLAY_VER(dev_priv) >= 11)
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icl_exec_gpio(connector, gpio_source, gpio_index, value);
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else if (IS_VALLEYVIEW(dev_priv))
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vlv_exec_gpio(connector, gpio_source, gpio_number, value);
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else if (IS_CHERRYVIEW(dev_priv))
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chv_exec_gpio(connector, gpio_source, gpio_number, value);
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else
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bxt_exec_gpio(connector, gpio_source, gpio_index, value);
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return data;
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}
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#ifdef CONFIG_ACPI
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static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
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{
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struct i2c_adapter_lookup *lookup = data;
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struct intel_dsi *intel_dsi = lookup->intel_dsi;
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struct acpi_resource_i2c_serialbus *sb;
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struct i2c_adapter *adapter;
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acpi_handle adapter_handle;
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acpi_status status;
|
|
|
|
if (!i2c_acpi_get_i2c_resource(ares, &sb))
|
|
return 1;
|
|
|
|
if (lookup->slave_addr != sb->slave_address)
|
|
return 1;
|
|
|
|
status = acpi_get_handle(lookup->dev_handle,
|
|
sb->resource_source.string_ptr,
|
|
&adapter_handle);
|
|
if (ACPI_FAILURE(status))
|
|
return 1;
|
|
|
|
adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
|
|
if (adapter)
|
|
intel_dsi->i2c_bus_num = adapter->nr;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
|
|
const u16 slave_addr)
|
|
{
|
|
struct drm_device *drm_dev = intel_dsi->base.base.dev;
|
|
struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev);
|
|
struct i2c_adapter_lookup lookup = {
|
|
.slave_addr = slave_addr,
|
|
.intel_dsi = intel_dsi,
|
|
.dev_handle = acpi_device_handle(adev),
|
|
};
|
|
LIST_HEAD(resource_list);
|
|
|
|
acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup);
|
|
acpi_dev_free_resource_list(&resource_list);
|
|
}
|
|
#else
|
|
static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
|
|
const u16 slave_addr)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
|
|
{
|
|
struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
|
|
struct i2c_adapter *adapter;
|
|
struct i2c_msg msg;
|
|
int ret;
|
|
u8 vbt_i2c_bus_num = *(data + 2);
|
|
u16 slave_addr = *(u16 *)(data + 3);
|
|
u8 reg_offset = *(data + 5);
|
|
u8 payload_size = *(data + 6);
|
|
u8 *payload_data;
|
|
|
|
if (intel_dsi->i2c_bus_num < 0) {
|
|
intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
|
|
i2c_acpi_find_adapter(intel_dsi, slave_addr);
|
|
}
|
|
|
|
adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
|
|
if (!adapter) {
|
|
drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n");
|
|
goto err_bus;
|
|
}
|
|
|
|
payload_data = kzalloc(payload_size + 1, GFP_KERNEL);
|
|
if (!payload_data)
|
|
goto err_alloc;
|
|
|
|
payload_data[0] = reg_offset;
|
|
memcpy(&payload_data[1], (data + 7), payload_size);
|
|
|
|
msg.addr = slave_addr;
|
|
msg.flags = 0;
|
|
msg.len = payload_size + 1;
|
|
msg.buf = payload_data;
|
|
|
|
ret = i2c_transfer(adapter, &msg, 1);
|
|
if (ret < 0)
|
|
drm_err(&i915->drm,
|
|
"Failed to xfer payload of size (%u) to reg (%u)\n",
|
|
payload_size, reg_offset);
|
|
|
|
kfree(payload_data);
|
|
err_alloc:
|
|
i2c_put_adapter(adapter);
|
|
err_bus:
|
|
return data + payload_size + 7;
|
|
}
|
|
|
|
static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
|
|
{
|
|
struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
|
|
|
|
drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n");
|
|
|
|
return data + *(data + 5) + 6;
|
|
}
|
|
|
|
static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
|
|
{
|
|
struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
|
|
#ifdef CONFIG_PMIC_OPREGION
|
|
u32 value, mask, reg_address;
|
|
u16 i2c_address;
|
|
int ret;
|
|
|
|
/* byte 0 aka PMIC Flag is reserved */
|
|
i2c_address = get_unaligned_le16(data + 1);
|
|
reg_address = get_unaligned_le32(data + 3);
|
|
value = get_unaligned_le32(data + 7);
|
|
mask = get_unaligned_le32(data + 11);
|
|
|
|
ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
|
|
reg_address,
|
|
value, mask);
|
|
if (ret)
|
|
drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret);
|
|
#else
|
|
drm_err(&i915->drm,
|
|
"Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
|
|
#endif
|
|
|
|
return data + 15;
|
|
}
|
|
|
|
typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
|
|
const u8 *data);
|
|
static const fn_mipi_elem_exec exec_elem[] = {
|
|
[MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
|
|
[MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
|
|
[MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
|
|
[MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
|
|
[MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
|
|
[MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
|
|
};
|
|
|
|
/*
|
|
* MIPI Sequence from VBT #53 parsing logic
|
|
* We have already separated each seqence during bios parsing
|
|
* Following is generic execution function for any sequence
|
|
*/
|
|
|
|
static const char * const seq_name[] = {
|
|
[MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
|
|
[MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
|
|
[MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
|
|
[MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
|
|
[MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
|
|
[MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
|
|
[MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
|
|
[MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
|
|
[MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
|
|
[MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
|
|
[MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
|
|
};
|
|
|
|
static const char *sequence_name(enum mipi_seq seq_id)
|
|
{
|
|
if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
|
|
return seq_name[seq_id];
|
|
else
|
|
return "(unknown)";
|
|
}
|
|
|
|
static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
|
|
enum mipi_seq seq_id)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
|
|
struct intel_connector *connector = intel_dsi->attached_connector;
|
|
const u8 *data;
|
|
fn_mipi_elem_exec mipi_elem_exec;
|
|
|
|
if (drm_WARN_ON(&dev_priv->drm,
|
|
seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence)))
|
|
return;
|
|
|
|
data = connector->panel.vbt.dsi.sequence[seq_id];
|
|
if (!data)
|
|
return;
|
|
|
|
drm_WARN_ON(&dev_priv->drm, *data != seq_id);
|
|
|
|
drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",
|
|
seq_id, sequence_name(seq_id));
|
|
|
|
/* Skip Sequence Byte. */
|
|
data++;
|
|
|
|
/* Skip Size of Sequence. */
|
|
if (connector->panel.vbt.dsi.seq_version >= 3)
|
|
data += 4;
|
|
|
|
while (1) {
|
|
u8 operation_byte = *data++;
|
|
u8 operation_size = 0;
|
|
|
|
if (operation_byte == MIPI_SEQ_ELEM_END)
|
|
break;
|
|
|
|
if (operation_byte < ARRAY_SIZE(exec_elem))
|
|
mipi_elem_exec = exec_elem[operation_byte];
|
|
else
|
|
mipi_elem_exec = NULL;
|
|
|
|
/* Size of Operation. */
|
|
if (connector->panel.vbt.dsi.seq_version >= 3)
|
|
operation_size = *data++;
|
|
|
|
if (mipi_elem_exec) {
|
|
const u8 *next = data + operation_size;
|
|
|
|
data = mipi_elem_exec(intel_dsi, data);
|
|
|
|
/* Consistency check if we have size. */
|
|
if (operation_size && data != next) {
|
|
drm_err(&dev_priv->drm,
|
|
"Inconsistent operation size\n");
|
|
return;
|
|
}
|
|
} else if (operation_size) {
|
|
/* We have size, skip. */
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
"Unsupported MIPI operation byte %u\n",
|
|
operation_byte);
|
|
data += operation_size;
|
|
} else {
|
|
/* No size, can't skip without parsing. */
|
|
drm_err(&dev_priv->drm,
|
|
"Unsupported MIPI operation byte %u\n",
|
|
operation_byte);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
|
|
enum mipi_seq seq_id)
|
|
{
|
|
if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
|
|
gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
|
|
if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
|
|
gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
|
|
|
|
intel_dsi_vbt_exec(intel_dsi, seq_id);
|
|
|
|
if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
|
|
gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
|
|
if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
|
|
gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
|
|
}
|
|
|
|
void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
|
|
{
|
|
struct intel_connector *connector = intel_dsi->attached_connector;
|
|
|
|
/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
|
|
if (is_vid_mode(intel_dsi) && connector->panel.vbt.dsi.seq_version >= 3)
|
|
return;
|
|
|
|
msleep(msec);
|
|
}
|
|
|
|
void intel_dsi_log_params(struct intel_dsi *intel_dsi)
|
|
{
|
|
struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
|
|
|
|
drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk);
|
|
drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",
|
|
intel_dsi->pixel_overlap);
|
|
drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count);
|
|
drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
|
|
drm_dbg_kms(&i915->drm, "Video mode format %s\n",
|
|
intel_dsi->video_mode == NON_BURST_SYNC_PULSE ?
|
|
"non-burst with sync pulse" :
|
|
intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ?
|
|
"non-burst with sync events" :
|
|
intel_dsi->video_mode == BURST_MODE ?
|
|
"burst" : "<unknown>");
|
|
drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",
|
|
intel_dsi->burst_mode_ratio);
|
|
drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val);
|
|
drm_dbg_kms(&i915->drm, "Eot %s\n",
|
|
str_enabled_disabled(intel_dsi->eotp_pkt));
|
|
drm_dbg_kms(&i915->drm, "Clockstop %s\n",
|
|
str_enabled_disabled(!intel_dsi->clock_stop));
|
|
drm_dbg_kms(&i915->drm, "Mode %s\n",
|
|
intel_dsi->operation_mode ? "command" : "video");
|
|
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
|
|
drm_dbg_kms(&i915->drm,
|
|
"Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
|
|
else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
|
|
drm_dbg_kms(&i915->drm,
|
|
"Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
|
|
else
|
|
drm_dbg_kms(&i915->drm, "Dual link: NONE\n");
|
|
drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format);
|
|
drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div);
|
|
drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",
|
|
intel_dsi->lp_rx_timeout);
|
|
drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",
|
|
intel_dsi->turn_arnd_val);
|
|
drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count);
|
|
drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",
|
|
intel_dsi->hs_to_lp_count);
|
|
drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
|
|
drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
|
|
drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",
|
|
intel_dsi->clk_lp_to_hs_count);
|
|
drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",
|
|
intel_dsi->clk_hs_to_lp_count);
|
|
drm_dbg_kms(&i915->drm, "BTA %s\n",
|
|
str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
|
|
}
|
|
|
|
bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
|
|
{
|
|
struct drm_device *dev = intel_dsi->base.base.dev;
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
struct intel_connector *connector = intel_dsi->attached_connector;
|
|
struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
|
|
struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps;
|
|
struct drm_display_mode *mode = connector->panel.vbt.lfp_lvds_vbt_mode;
|
|
u16 burst_mode_ratio;
|
|
enum port port;
|
|
|
|
drm_dbg_kms(&dev_priv->drm, "\n");
|
|
|
|
intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
|
|
intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
|
|
intel_dsi->lane_count = mipi_config->lane_cnt + 1;
|
|
intel_dsi->pixel_format =
|
|
pixel_format_from_register_bits(
|
|
mipi_config->videomode_color_format << 7);
|
|
|
|
intel_dsi->dual_link = mipi_config->dual_link;
|
|
intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
|
|
intel_dsi->operation_mode = mipi_config->is_cmd_mode;
|
|
intel_dsi->video_mode = mipi_config->video_transfer_mode;
|
|
intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
|
|
intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
|
|
intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
|
|
intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
|
|
intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
|
|
intel_dsi->init_count = mipi_config->master_init_timer;
|
|
intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
|
|
intel_dsi->video_frmt_cfg_bits =
|
|
mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
|
|
intel_dsi->bgr_enabled = mipi_config->rgb_flip;
|
|
|
|
/* Starting point, adjusted depending on dual link and burst mode */
|
|
intel_dsi->pclk = mode->clock;
|
|
|
|
/* In dual link mode each port needs half of pixel clock */
|
|
if (intel_dsi->dual_link) {
|
|
intel_dsi->pclk /= 2;
|
|
|
|
/* we can enable pixel_overlap if needed by panel. In this
|
|
* case we need to increase the pixelclock for extra pixels
|
|
*/
|
|
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
|
|
intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
|
|
}
|
|
}
|
|
|
|
/* Burst Mode Ratio
|
|
* Target ddr frequency from VBT / non burst ddr freq
|
|
* multiply by 100 to preserve remainder
|
|
*/
|
|
if (intel_dsi->video_mode == BURST_MODE) {
|
|
if (mipi_config->target_burst_mode_freq) {
|
|
u32 bitrate = intel_dsi_bitrate(intel_dsi);
|
|
|
|
/*
|
|
* Sometimes the VBT contains a slightly lower clock,
|
|
* then the bitrate we have calculated, in this case
|
|
* just replace it with the calculated bitrate.
|
|
*/
|
|
if (mipi_config->target_burst_mode_freq < bitrate &&
|
|
intel_fuzzy_clock_check(
|
|
mipi_config->target_burst_mode_freq,
|
|
bitrate))
|
|
mipi_config->target_burst_mode_freq = bitrate;
|
|
|
|
if (mipi_config->target_burst_mode_freq < bitrate) {
|
|
drm_err(&dev_priv->drm,
|
|
"Burst mode freq is less than computed\n");
|
|
return false;
|
|
}
|
|
|
|
burst_mode_ratio = DIV_ROUND_UP(
|
|
mipi_config->target_burst_mode_freq * 100,
|
|
bitrate);
|
|
|
|
intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
|
|
} else {
|
|
drm_err(&dev_priv->drm,
|
|
"Burst mode target is not set\n");
|
|
return false;
|
|
}
|
|
} else
|
|
burst_mode_ratio = 100;
|
|
|
|
intel_dsi->burst_mode_ratio = burst_mode_ratio;
|
|
|
|
/* delays in VBT are in unit of 100us, so need to convert
|
|
* here in ms
|
|
* Delay (100us) * 100 /1000 = Delay / 10 (ms) */
|
|
intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
|
|
intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
|
|
intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
|
|
intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
|
|
intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
|
|
|
|
intel_dsi->i2c_bus_num = -1;
|
|
|
|
/* a regular driver would get the device in probe */
|
|
for_each_dsi_port(port, intel_dsi->ports) {
|
|
mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
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/*
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* On some BYT/CHT devs some sequences are incomplete and we need to manually
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* control some GPIOs. We need to add a GPIO lookup table before we get these.
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* If the GOP did not initialize the panel (HDMI inserted) we may need to also
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* change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
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*/
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static struct gpiod_lookup_table pmic_panel_gpio_table = {
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/* Intel GFX is consumer */
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.dev_id = "0000:00:02.0",
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.table = {
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/* Panel EN/DISABLE */
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GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
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{ }
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},
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};
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static struct gpiod_lookup_table soc_panel_gpio_table = {
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.dev_id = "0000:00:02.0",
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.table = {
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GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
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GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
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{ }
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},
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};
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static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
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PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
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"pwm0_grp", "pwm"),
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};
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void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
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{
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struct drm_device *dev = intel_dsi->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_connector *connector = intel_dsi->attached_connector;
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struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
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enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
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bool want_backlight_gpio = false;
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bool want_panel_gpio = false;
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struct pinctrl *pinctrl;
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int ret;
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if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
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mipi_config->pwm_blc == PPS_BLC_PMIC) {
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gpiod_add_lookup_table(&pmic_panel_gpio_table);
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want_panel_gpio = true;
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}
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if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
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gpiod_add_lookup_table(&soc_panel_gpio_table);
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want_panel_gpio = true;
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want_backlight_gpio = true;
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/* Ensure PWM0 pin is muxed as PWM instead of GPIO */
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ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
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ARRAY_SIZE(soc_pwm_pinctrl_map));
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if (ret)
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drm_err(&dev_priv->drm,
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"Failed to register pwm0 pinmux mapping\n");
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pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
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if (IS_ERR(pinctrl))
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drm_err(&dev_priv->drm,
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"Failed to set pinmux to PWM\n");
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}
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if (want_panel_gpio) {
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intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
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if (IS_ERR(intel_dsi->gpio_panel)) {
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drm_err(&dev_priv->drm,
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"Failed to own gpio for panel control\n");
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intel_dsi->gpio_panel = NULL;
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}
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}
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if (want_backlight_gpio) {
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intel_dsi->gpio_backlight =
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gpiod_get(dev->dev, "backlight", flags);
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if (IS_ERR(intel_dsi->gpio_backlight)) {
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drm_err(&dev_priv->drm,
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"Failed to own gpio for backlight control\n");
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intel_dsi->gpio_backlight = NULL;
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}
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}
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}
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void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
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{
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struct drm_device *dev = intel_dsi->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_connector *connector = intel_dsi->attached_connector;
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struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
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if (intel_dsi->gpio_panel) {
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gpiod_put(intel_dsi->gpio_panel);
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intel_dsi->gpio_panel = NULL;
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}
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if (intel_dsi->gpio_backlight) {
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gpiod_put(intel_dsi->gpio_backlight);
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intel_dsi->gpio_backlight = NULL;
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}
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if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
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mipi_config->pwm_blc == PPS_BLC_PMIC)
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gpiod_remove_lookup_table(&pmic_panel_gpio_table);
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if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) {
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pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
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gpiod_remove_lookup_table(&soc_panel_gpio_table);
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|
}
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}
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