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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
![Jani Nikula](/assets/img/avatar_default.png)
Turns out many of the files that need i915_reg.h get it implicitly via {display/intel_de.h, gt/intel_context.h} -> i915_trace.h -> i915_irq.h -> i915_reg.h. Since i915_trace.h doesn't actually need i915_irq.h, makes sense to drop it, but that requires adding quite a few new includes all over the place. Prefer including i915_reg.h where needed instead of adding another implicit include, because eventually we'll want to split up i915_reg.h and only include the specific registers at each place. Also some places actually needed i915_irq.h too. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6e78a2e0ac1bffaf5af3b5ccc21dff05e6518cef.1668008071.git.jani.nikula@intel.com
750 lines
22 KiB
C
750 lines
22 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*
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* Read out the current hardware modeset state, and sanitize it to the current
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* state.
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*/
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#include <drm/drm_atomic_uapi.h>
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#include <drm/drm_atomic_state_helper.h>
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_atomic.h"
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#include "intel_bw.h"
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#include "intel_color.h"
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#include "intel_crtc.h"
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#include "intel_crtc_state_dump.h"
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#include "intel_ddi.h"
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#include "intel_de.h"
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#include "intel_display.h"
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#include "intel_display_power.h"
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#include "intel_display_types.h"
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#include "intel_modeset_setup.h"
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#include "intel_pch_display.h"
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#include "intel_pm.h"
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#include "skl_watermark.h"
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static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
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struct drm_modeset_acquire_ctx *ctx)
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{
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struct intel_encoder *encoder;
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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struct intel_bw_state *bw_state =
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to_intel_bw_state(i915->display.bw.obj.state);
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struct intel_cdclk_state *cdclk_state =
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to_intel_cdclk_state(i915->display.cdclk.obj.state);
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struct intel_dbuf_state *dbuf_state =
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to_intel_dbuf_state(i915->display.dbuf.obj.state);
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struct intel_crtc_state *crtc_state =
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to_intel_crtc_state(crtc->base.state);
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struct intel_plane *plane;
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struct drm_atomic_state *state;
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struct intel_crtc_state *temp_crtc_state;
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enum pipe pipe = crtc->pipe;
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int ret;
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if (!crtc_state->hw.active)
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return;
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for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
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const struct intel_plane_state *plane_state =
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to_intel_plane_state(plane->base.state);
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if (plane_state->uapi.visible)
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intel_plane_disable_noatomic(crtc, plane);
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}
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state = drm_atomic_state_alloc(&i915->drm);
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if (!state) {
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drm_dbg_kms(&i915->drm,
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"failed to disable [CRTC:%d:%s], out of memory",
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crtc->base.base.id, crtc->base.name);
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return;
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}
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state->acquire_ctx = ctx;
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/* Everything's already locked, -EDEADLK can't happen. */
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temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
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ret = drm_atomic_add_affected_connectors(state, &crtc->base);
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drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
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i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
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drm_atomic_state_put(state);
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drm_dbg_kms(&i915->drm,
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"[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
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crtc->base.base.id, crtc->base.name);
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crtc->active = false;
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crtc->base.enabled = false;
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drm_WARN_ON(&i915->drm,
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drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
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crtc_state->uapi.active = false;
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crtc_state->uapi.connector_mask = 0;
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crtc_state->uapi.encoder_mask = 0;
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intel_crtc_free_hw_state(crtc_state);
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memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
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for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder)
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encoder->base.crtc = NULL;
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intel_fbc_disable(crtc);
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intel_update_watermarks(i915);
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intel_disable_shared_dpll(crtc_state);
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intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains);
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cdclk_state->min_cdclk[pipe] = 0;
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cdclk_state->min_voltage_level[pipe] = 0;
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cdclk_state->active_pipes &= ~BIT(pipe);
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dbuf_state->active_pipes &= ~BIT(pipe);
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bw_state->data_rate[pipe] = 0;
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bw_state->num_active_planes[pipe] = 0;
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}
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static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
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{
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struct intel_connector *connector;
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struct drm_connector_list_iter conn_iter;
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drm_connector_list_iter_begin(&i915->drm, &conn_iter);
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for_each_intel_connector_iter(connector, &conn_iter) {
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struct drm_connector_state *conn_state = connector->base.state;
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struct intel_encoder *encoder =
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to_intel_encoder(connector->base.encoder);
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if (conn_state->crtc)
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drm_connector_put(&connector->base);
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if (encoder) {
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struct intel_crtc *crtc =
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to_intel_crtc(encoder->base.crtc);
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const struct intel_crtc_state *crtc_state =
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to_intel_crtc_state(crtc->base.state);
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conn_state->best_encoder = &encoder->base;
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conn_state->crtc = &crtc->base;
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conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
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drm_connector_get(&connector->base);
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} else {
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conn_state->best_encoder = NULL;
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conn_state->crtc = NULL;
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}
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}
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drm_connector_list_iter_end(&conn_iter);
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}
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static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
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{
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if (intel_crtc_is_bigjoiner_slave(crtc_state))
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return;
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crtc_state->uapi.enable = crtc_state->hw.enable;
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crtc_state->uapi.active = crtc_state->hw.active;
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drm_WARN_ON(crtc_state->uapi.crtc->dev,
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drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
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crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
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crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
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/* assume 1:1 mapping */
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drm_property_replace_blob(&crtc_state->hw.degamma_lut,
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crtc_state->pre_csc_lut);
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drm_property_replace_blob(&crtc_state->hw.gamma_lut,
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crtc_state->post_csc_lut);
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drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
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crtc_state->hw.degamma_lut);
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drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
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crtc_state->hw.gamma_lut);
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drm_property_replace_blob(&crtc_state->uapi.ctm,
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crtc_state->hw.ctm);
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}
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static void
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intel_sanitize_plane_mapping(struct drm_i915_private *i915)
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{
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struct intel_crtc *crtc;
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if (DISPLAY_VER(i915) >= 4)
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return;
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for_each_intel_crtc(&i915->drm, crtc) {
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struct intel_plane *plane =
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to_intel_plane(crtc->base.primary);
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struct intel_crtc *plane_crtc;
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enum pipe pipe;
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if (!plane->get_hw_state(plane, &pipe))
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continue;
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if (pipe == crtc->pipe)
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continue;
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drm_dbg_kms(&i915->drm,
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"[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
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plane->base.base.id, plane->base.name);
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plane_crtc = intel_crtc_for_pipe(i915, pipe);
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intel_plane_disable_noatomic(plane_crtc, plane);
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}
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}
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static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct intel_encoder *encoder;
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for_each_encoder_on_crtc(dev, &crtc->base, encoder)
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return true;
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return false;
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}
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static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct drm_connector_list_iter conn_iter;
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struct intel_connector *connector;
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struct intel_connector *found_connector = NULL;
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drm_connector_list_iter_begin(&i915->drm, &conn_iter);
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for_each_intel_connector_iter(connector, &conn_iter) {
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if (&encoder->base == connector->base.encoder) {
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found_connector = connector;
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break;
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}
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}
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drm_connector_list_iter_end(&conn_iter);
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return found_connector;
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}
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static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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if (!crtc_state->hw.active && !HAS_GMCH(i915))
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return;
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/*
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* We start out with underrun reporting disabled to avoid races.
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* For correct bookkeeping mark this on active crtcs.
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*
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* Also on gmch platforms we dont have any hardware bits to
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* disable the underrun reporting. Which means we need to start
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* out with underrun reporting disabled also on inactive pipes,
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* since otherwise we'll complain about the garbage we read when
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* e.g. coming up after runtime pm.
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*
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* No protection against concurrent access is required - at
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* worst a fifo underrun happens which also sets this to false.
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*/
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crtc->cpu_fifo_underrun_disabled = true;
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/*
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* We track the PCH trancoder underrun reporting state
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* within the crtc. With crtc for pipe A housing the underrun
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* reporting state for PCH transcoder A, crtc for pipe B housing
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* it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
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* and marking underrun reporting as disabled for the non-existing
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* PCH transcoders B and C would prevent enabling the south
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* error interrupt (see cpt_can_enable_serr_int()).
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*/
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if (intel_has_pch_trancoder(i915, crtc->pipe))
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crtc->pch_fifo_underrun_disabled = true;
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}
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static void intel_sanitize_crtc(struct intel_crtc *crtc,
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struct drm_modeset_acquire_ctx *ctx)
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{
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
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if (crtc_state->hw.active) {
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struct intel_plane *plane;
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/* Disable everything but the primary plane */
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for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
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const struct intel_plane_state *plane_state =
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to_intel_plane_state(plane->base.state);
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if (plane_state->uapi.visible &&
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plane->base.type != DRM_PLANE_TYPE_PRIMARY)
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intel_plane_disable_noatomic(crtc, plane);
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}
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/* Disable any background color/etc. set by the BIOS */
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intel_color_commit_noarm(crtc_state);
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intel_color_commit_arm(crtc_state);
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}
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/*
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* Adjust the state of the output pipe according to whether we have
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* active connectors/encoders.
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*/
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if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
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!intel_crtc_is_bigjoiner_slave(crtc_state))
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intel_crtc_disable_noatomic(crtc, ctx);
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}
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static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
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/*
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* Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
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* the hardware when a high res displays plugged in. DPLL P
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* divider is zero, and the pipe timings are bonkers. We'll
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* try to disable everything in that case.
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*
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* FIXME would be nice to be able to sanitize this state
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* without several WARNs, but for now let's take the easy
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* road.
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*/
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return IS_SANDYBRIDGE(i915) &&
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crtc_state->hw.active &&
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crtc_state->shared_dpll &&
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crtc_state->port_clock == 0;
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}
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static void intel_sanitize_encoder(struct intel_encoder *encoder)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_connector *connector;
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struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
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struct intel_crtc_state *crtc_state = crtc ?
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to_intel_crtc_state(crtc->base.state) : NULL;
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/*
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* We need to check both for a crtc link (meaning that the encoder is
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* active and trying to read from a pipe) and the pipe itself being
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* active.
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*/
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bool has_active_crtc = crtc_state &&
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crtc_state->hw.active;
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if (crtc_state && has_bogus_dpll_config(crtc_state)) {
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drm_dbg_kms(&i915->drm,
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"BIOS has misprogrammed the hardware. Disabling pipe %c\n",
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pipe_name(crtc->pipe));
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has_active_crtc = false;
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}
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connector = intel_encoder_find_connector(encoder);
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if (connector && !has_active_crtc) {
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drm_dbg_kms(&i915->drm,
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"[ENCODER:%d:%s] has active connectors but no active pipe!\n",
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encoder->base.base.id,
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encoder->base.name);
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/*
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* Connector is active, but has no active pipe. This is fallout
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* from our resume register restoring. Disable the encoder
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* manually again.
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*/
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if (crtc_state) {
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struct drm_encoder *best_encoder;
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drm_dbg_kms(&i915->drm,
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"[ENCODER:%d:%s] manually disabled\n",
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encoder->base.base.id,
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encoder->base.name);
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/* avoid oopsing in case the hooks consult best_encoder */
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best_encoder = connector->base.state->best_encoder;
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connector->base.state->best_encoder = &encoder->base;
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/* FIXME NULL atomic state passed! */
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if (encoder->disable)
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encoder->disable(NULL, encoder, crtc_state,
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connector->base.state);
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if (encoder->post_disable)
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encoder->post_disable(NULL, encoder, crtc_state,
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connector->base.state);
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connector->base.state->best_encoder = best_encoder;
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}
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encoder->base.crtc = NULL;
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/*
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* Inconsistent output/port/pipe state happens presumably due to
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* a bug in one of the get_hw_state functions. Or someplace else
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* in our code, like the register restore mess on resume. Clamp
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* things to off as a safer default.
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*/
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connector->base.dpms = DRM_MODE_DPMS_OFF;
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connector->base.encoder = NULL;
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}
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/* notify opregion of the sanitized encoder state */
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intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
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if (HAS_DDI(i915))
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intel_ddi_sanitize_encoder_pll_mapping(encoder);
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}
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/* FIXME read out full plane state for all planes */
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static void readout_plane_state(struct drm_i915_private *i915)
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{
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struct intel_plane *plane;
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struct intel_crtc *crtc;
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for_each_intel_plane(&i915->drm, plane) {
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struct intel_plane_state *plane_state =
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to_intel_plane_state(plane->base.state);
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struct intel_crtc_state *crtc_state;
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enum pipe pipe = PIPE_A;
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bool visible;
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visible = plane->get_hw_state(plane, &pipe);
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crtc = intel_crtc_for_pipe(i915, pipe);
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crtc_state = to_intel_crtc_state(crtc->base.state);
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intel_set_plane_visible(crtc_state, plane_state, visible);
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drm_dbg_kms(&i915->drm,
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"[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
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plane->base.base.id, plane->base.name,
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str_enabled_disabled(visible), pipe_name(pipe));
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}
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for_each_intel_crtc(&i915->drm, crtc) {
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struct intel_crtc_state *crtc_state =
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to_intel_crtc_state(crtc->base.state);
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intel_plane_fixup_bitmasks(crtc_state);
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}
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}
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static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
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{
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struct intel_cdclk_state *cdclk_state =
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to_intel_cdclk_state(i915->display.cdclk.obj.state);
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struct intel_dbuf_state *dbuf_state =
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to_intel_dbuf_state(i915->display.dbuf.obj.state);
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enum pipe pipe;
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struct intel_crtc *crtc;
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struct intel_encoder *encoder;
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struct intel_connector *connector;
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struct drm_connector_list_iter conn_iter;
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u8 active_pipes = 0;
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for_each_intel_crtc(&i915->drm, crtc) {
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struct intel_crtc_state *crtc_state =
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to_intel_crtc_state(crtc->base.state);
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__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
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intel_crtc_free_hw_state(crtc_state);
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intel_crtc_state_reset(crtc_state, crtc);
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intel_crtc_get_pipe_config(crtc_state);
|
|
|
|
crtc_state->hw.enable = crtc_state->hw.active;
|
|
|
|
crtc->base.enabled = crtc_state->hw.enable;
|
|
crtc->active = crtc_state->hw.active;
|
|
|
|
if (crtc_state->hw.active)
|
|
active_pipes |= BIT(crtc->pipe);
|
|
|
|
drm_dbg_kms(&i915->drm,
|
|
"[CRTC:%d:%s] hw state readout: %s\n",
|
|
crtc->base.base.id, crtc->base.name,
|
|
str_enabled_disabled(crtc_state->hw.active));
|
|
}
|
|
|
|
cdclk_state->active_pipes = active_pipes;
|
|
dbuf_state->active_pipes = active_pipes;
|
|
|
|
readout_plane_state(i915);
|
|
|
|
for_each_intel_encoder(&i915->drm, encoder) {
|
|
struct intel_crtc_state *crtc_state = NULL;
|
|
|
|
pipe = 0;
|
|
|
|
if (encoder->get_hw_state(encoder, &pipe)) {
|
|
crtc = intel_crtc_for_pipe(i915, pipe);
|
|
crtc_state = to_intel_crtc_state(crtc->base.state);
|
|
|
|
encoder->base.crtc = &crtc->base;
|
|
intel_encoder_get_config(encoder, crtc_state);
|
|
|
|
/* read out to slave crtc as well for bigjoiner */
|
|
if (crtc_state->bigjoiner_pipes) {
|
|
struct intel_crtc *slave_crtc;
|
|
|
|
/* encoder should read be linked to bigjoiner master */
|
|
WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
|
|
|
|
for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
|
|
intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
|
|
struct intel_crtc_state *slave_crtc_state;
|
|
|
|
slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
|
|
intel_encoder_get_config(encoder, slave_crtc_state);
|
|
}
|
|
}
|
|
} else {
|
|
encoder->base.crtc = NULL;
|
|
}
|
|
|
|
if (encoder->sync_state)
|
|
encoder->sync_state(encoder, crtc_state);
|
|
|
|
drm_dbg_kms(&i915->drm,
|
|
"[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
|
|
encoder->base.base.id, encoder->base.name,
|
|
str_enabled_disabled(encoder->base.crtc),
|
|
pipe_name(pipe));
|
|
}
|
|
|
|
intel_dpll_readout_hw_state(i915);
|
|
|
|
drm_connector_list_iter_begin(&i915->drm, &conn_iter);
|
|
for_each_intel_connector_iter(connector, &conn_iter) {
|
|
if (connector->get_hw_state(connector)) {
|
|
struct intel_crtc_state *crtc_state;
|
|
struct intel_crtc *crtc;
|
|
|
|
connector->base.dpms = DRM_MODE_DPMS_ON;
|
|
|
|
encoder = intel_attached_encoder(connector);
|
|
connector->base.encoder = &encoder->base;
|
|
|
|
crtc = to_intel_crtc(encoder->base.crtc);
|
|
crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
|
|
|
|
if (crtc_state && crtc_state->hw.active) {
|
|
/*
|
|
* This has to be done during hardware readout
|
|
* because anything calling .crtc_disable may
|
|
* rely on the connector_mask being accurate.
|
|
*/
|
|
crtc_state->uapi.connector_mask |=
|
|
drm_connector_mask(&connector->base);
|
|
crtc_state->uapi.encoder_mask |=
|
|
drm_encoder_mask(&encoder->base);
|
|
}
|
|
} else {
|
|
connector->base.dpms = DRM_MODE_DPMS_OFF;
|
|
connector->base.encoder = NULL;
|
|
}
|
|
drm_dbg_kms(&i915->drm,
|
|
"[CONNECTOR:%d:%s] hw state readout: %s\n",
|
|
connector->base.base.id, connector->base.name,
|
|
str_enabled_disabled(connector->base.encoder));
|
|
}
|
|
drm_connector_list_iter_end(&conn_iter);
|
|
|
|
for_each_intel_crtc(&i915->drm, crtc) {
|
|
struct intel_bw_state *bw_state =
|
|
to_intel_bw_state(i915->display.bw.obj.state);
|
|
struct intel_crtc_state *crtc_state =
|
|
to_intel_crtc_state(crtc->base.state);
|
|
struct intel_plane *plane;
|
|
int min_cdclk = 0;
|
|
|
|
if (crtc_state->hw.active) {
|
|
/*
|
|
* The initial mode needs to be set in order to keep
|
|
* the atomic core happy. It wants a valid mode if the
|
|
* crtc's enabled, so we do the above call.
|
|
*
|
|
* But we don't set all the derived state fully, hence
|
|
* set a flag to indicate that a full recalculation is
|
|
* needed on the next commit.
|
|
*/
|
|
crtc_state->inherited = true;
|
|
|
|
intel_crtc_update_active_timings(crtc_state);
|
|
|
|
intel_crtc_copy_hw_to_uapi_state(crtc_state);
|
|
}
|
|
|
|
for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
|
|
const struct intel_plane_state *plane_state =
|
|
to_intel_plane_state(plane->base.state);
|
|
|
|
/*
|
|
* FIXME don't have the fb yet, so can't
|
|
* use intel_plane_data_rate() :(
|
|
*/
|
|
if (plane_state->uapi.visible)
|
|
crtc_state->data_rate[plane->id] =
|
|
4 * crtc_state->pixel_rate;
|
|
/*
|
|
* FIXME don't have the fb yet, so can't
|
|
* use plane->min_cdclk() :(
|
|
*/
|
|
if (plane_state->uapi.visible && plane->min_cdclk) {
|
|
if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10)
|
|
crtc_state->min_cdclk[plane->id] =
|
|
DIV_ROUND_UP(crtc_state->pixel_rate, 2);
|
|
else
|
|
crtc_state->min_cdclk[plane->id] =
|
|
crtc_state->pixel_rate;
|
|
}
|
|
drm_dbg_kms(&i915->drm,
|
|
"[PLANE:%d:%s] min_cdclk %d kHz\n",
|
|
plane->base.base.id, plane->base.name,
|
|
crtc_state->min_cdclk[plane->id]);
|
|
}
|
|
|
|
if (crtc_state->hw.active) {
|
|
min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
|
|
if (drm_WARN_ON(&i915->drm, min_cdclk < 0))
|
|
min_cdclk = 0;
|
|
}
|
|
|
|
cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
|
|
cdclk_state->min_voltage_level[crtc->pipe] =
|
|
crtc_state->min_voltage_level;
|
|
|
|
intel_bw_crtc_update(bw_state, crtc_state);
|
|
}
|
|
}
|
|
|
|
static void
|
|
get_encoder_power_domains(struct drm_i915_private *i915)
|
|
{
|
|
struct intel_encoder *encoder;
|
|
|
|
for_each_intel_encoder(&i915->drm, encoder) {
|
|
struct intel_crtc_state *crtc_state;
|
|
|
|
if (!encoder->get_power_domains)
|
|
continue;
|
|
|
|
/*
|
|
* MST-primary and inactive encoders don't have a crtc state
|
|
* and neither of these require any power domain references.
|
|
*/
|
|
if (!encoder->base.crtc)
|
|
continue;
|
|
|
|
crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
|
|
encoder->get_power_domains(encoder, crtc_state);
|
|
}
|
|
}
|
|
|
|
static void intel_early_display_was(struct drm_i915_private *i915)
|
|
{
|
|
/*
|
|
* Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
|
|
* Also known as Wa_14010480278.
|
|
*/
|
|
if (IS_DISPLAY_VER(i915, 10, 12))
|
|
intel_de_write(i915, GEN9_CLKGATE_DIS_0,
|
|
intel_de_read(i915, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
|
|
|
|
if (IS_HASWELL(i915)) {
|
|
/*
|
|
* WaRsPkgCStateDisplayPMReq:hsw
|
|
* System hang if this isn't done before disabling all planes!
|
|
*/
|
|
intel_de_write(i915, CHICKEN_PAR1_1,
|
|
intel_de_read(i915, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
|
|
}
|
|
|
|
if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
|
|
/* Display WA #1142:kbl,cfl,cml */
|
|
intel_de_rmw(i915, CHICKEN_PAR1_1,
|
|
KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
|
|
intel_de_rmw(i915, CHICKEN_MISC_2,
|
|
KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
|
|
KBL_ARB_FILL_SPARE_14);
|
|
}
|
|
}
|
|
|
|
void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
|
|
struct drm_modeset_acquire_ctx *ctx)
|
|
{
|
|
struct intel_encoder *encoder;
|
|
struct intel_crtc *crtc;
|
|
intel_wakeref_t wakeref;
|
|
|
|
wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
|
|
|
|
intel_early_display_was(i915);
|
|
intel_modeset_readout_hw_state(i915);
|
|
|
|
/* HW state is read out, now we need to sanitize this mess. */
|
|
get_encoder_power_domains(i915);
|
|
|
|
intel_pch_sanitize(i915);
|
|
|
|
/*
|
|
* intel_sanitize_plane_mapping() may need to do vblank
|
|
* waits, so we need vblank interrupts restored beforehand.
|
|
*/
|
|
for_each_intel_crtc(&i915->drm, crtc) {
|
|
struct intel_crtc_state *crtc_state =
|
|
to_intel_crtc_state(crtc->base.state);
|
|
|
|
intel_sanitize_fifo_underrun_reporting(crtc_state);
|
|
|
|
drm_crtc_vblank_reset(&crtc->base);
|
|
|
|
if (crtc_state->hw.active)
|
|
intel_crtc_vblank_on(crtc_state);
|
|
}
|
|
|
|
intel_fbc_sanitize(i915);
|
|
|
|
intel_sanitize_plane_mapping(i915);
|
|
|
|
for_each_intel_encoder(&i915->drm, encoder)
|
|
intel_sanitize_encoder(encoder);
|
|
|
|
for_each_intel_crtc(&i915->drm, crtc) {
|
|
struct intel_crtc_state *crtc_state =
|
|
to_intel_crtc_state(crtc->base.state);
|
|
|
|
intel_sanitize_crtc(crtc, ctx);
|
|
intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
|
|
}
|
|
|
|
intel_modeset_update_connector_atomic_state(i915);
|
|
|
|
intel_dpll_sanitize_state(i915);
|
|
|
|
if (IS_G4X(i915)) {
|
|
g4x_wm_get_hw_state(i915);
|
|
g4x_wm_sanitize(i915);
|
|
} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
|
|
vlv_wm_get_hw_state(i915);
|
|
vlv_wm_sanitize(i915);
|
|
} else if (DISPLAY_VER(i915) >= 9) {
|
|
skl_wm_get_hw_state(i915);
|
|
skl_wm_sanitize(i915);
|
|
} else if (HAS_PCH_SPLIT(i915)) {
|
|
ilk_wm_get_hw_state(i915);
|
|
}
|
|
|
|
for_each_intel_crtc(&i915->drm, crtc) {
|
|
struct intel_crtc_state *crtc_state =
|
|
to_intel_crtc_state(crtc->base.state);
|
|
struct intel_power_domain_mask put_domains;
|
|
|
|
intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
|
|
if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
|
|
intel_modeset_put_crtc_power_domains(crtc, &put_domains);
|
|
}
|
|
|
|
intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
|
|
|
|
intel_power_domains_sanitize_state(i915);
|
|
}
|