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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
![Jani Nikula](/assets/img/avatar_default.png)
Turns out many of the files that need i915_reg.h get it implicitly via {display/intel_de.h, gt/intel_context.h} -> i915_trace.h -> i915_irq.h -> i915_reg.h. Since i915_trace.h doesn't actually need i915_irq.h, makes sense to drop it, but that requires adding quite a few new includes all over the place. Prefer including i915_reg.h where needed instead of adding another implicit include, because eventually we'll want to split up i915_reg.h and only include the specific registers at each place. Also some places actually needed i915_irq.h too. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6e78a2e0ac1bffaf5af3b5ccc21dff05e6518cef.1668008071.git.jani.nikula@intel.com
680 lines
18 KiB
C
680 lines
18 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#include "i915_reg.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_panel.h"
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#include "intel_pch_refclk.h"
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#include "intel_sbi.h"
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static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv)
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{
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u32 tmp;
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tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
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tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
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intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
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if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
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FDI_MPHY_IOSFSB_RESET_STATUS, 100))
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drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
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tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
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tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
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intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
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if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
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FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
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drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
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}
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/* WaMPhyProgramming:hsw */
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static void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
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{
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u32 tmp;
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lpt_fdi_reset_mphy(dev_priv);
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tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
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tmp &= ~(0xFF << 24);
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tmp |= (0x12 << 24);
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intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
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tmp |= (1 << 11);
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intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
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tmp |= (1 << 11);
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intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
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tmp |= (1 << 24) | (1 << 21) | (1 << 18);
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intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
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tmp |= (1 << 24) | (1 << 21) | (1 << 18);
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intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
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tmp &= ~(7 << 13);
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tmp |= (5 << 13);
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intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
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tmp &= ~(7 << 13);
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tmp |= (5 << 13);
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intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
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tmp &= ~0xFF;
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tmp |= 0x1C;
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intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
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tmp &= ~0xFF;
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tmp |= 0x1C;
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intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
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tmp &= ~(0xFF << 16);
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tmp |= (0x1C << 16);
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intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
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tmp &= ~(0xFF << 16);
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tmp |= (0x1C << 16);
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intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
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tmp |= (1 << 27);
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intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
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tmp |= (1 << 27);
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intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
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tmp &= ~(0xF << 28);
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tmp |= (4 << 28);
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intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
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tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
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tmp &= ~(0xF << 28);
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tmp |= (4 << 28);
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intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
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}
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void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
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{
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u32 temp;
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intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
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mutex_lock(&dev_priv->sb_lock);
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temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
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temp |= SBI_SSCCTL_DISABLE;
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intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
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mutex_unlock(&dev_priv->sb_lock);
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}
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struct iclkip_params {
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u32 iclk_virtual_root_freq;
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u32 iclk_pi_range;
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u32 divsel, phaseinc, auxdiv, phasedir, desired_divisor;
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};
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static void iclkip_params_init(struct iclkip_params *p)
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{
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memset(p, 0, sizeof(*p));
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p->iclk_virtual_root_freq = 172800 * 1000;
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p->iclk_pi_range = 64;
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}
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static int lpt_iclkip_freq(struct iclkip_params *p)
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{
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return DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
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p->desired_divisor << p->auxdiv);
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}
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static void lpt_compute_iclkip(struct iclkip_params *p, int clock)
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{
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iclkip_params_init(p);
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/* The iCLK virtual clock root frequency is in MHz,
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* but the adjusted_mode->crtc_clock in KHz. To get the
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* divisors, it is necessary to divide one by another, so we
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* convert the virtual clock precision to KHz here for higher
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* precision.
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*/
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for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) {
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p->desired_divisor = DIV_ROUND_CLOSEST(p->iclk_virtual_root_freq,
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clock << p->auxdiv);
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p->divsel = (p->desired_divisor / p->iclk_pi_range) - 2;
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p->phaseinc = p->desired_divisor % p->iclk_pi_range;
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/*
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* Near 20MHz is a corner case which is
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* out of range for the 7-bit divisor
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*/
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if (p->divsel <= 0x7f)
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break;
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}
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}
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int lpt_iclkip(const struct intel_crtc_state *crtc_state)
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{
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struct iclkip_params p;
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lpt_compute_iclkip(&p, crtc_state->hw.adjusted_mode.crtc_clock);
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return lpt_iclkip_freq(&p);
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}
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/* Program iCLKIP clock to the desired frequency */
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void lpt_program_iclkip(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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int clock = crtc_state->hw.adjusted_mode.crtc_clock;
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struct iclkip_params p;
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u32 temp;
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lpt_disable_iclkip(dev_priv);
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lpt_compute_iclkip(&p, clock);
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drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);
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/* This should not happen with any sane values */
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drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
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~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
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drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
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~SBI_SSCDIVINTPHASE_INCVAL_MASK);
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drm_dbg_kms(&dev_priv->drm,
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"iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
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clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc);
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mutex_lock(&dev_priv->sb_lock);
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/* Program SSCDIVINTPHASE6 */
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temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
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temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
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temp |= SBI_SSCDIVINTPHASE_DIVSEL(p.divsel);
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temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
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temp |= SBI_SSCDIVINTPHASE_INCVAL(p.phaseinc);
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temp |= SBI_SSCDIVINTPHASE_DIR(p.phasedir);
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temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
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intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
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/* Program SSCAUXDIV */
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temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
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temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
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temp |= SBI_SSCAUXDIV_FINALDIV2SEL(p.auxdiv);
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intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
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/* Enable modulator and associated divider */
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temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
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temp &= ~SBI_SSCCTL_DISABLE;
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intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
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mutex_unlock(&dev_priv->sb_lock);
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/* Wait for initialization time */
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udelay(24);
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intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
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}
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int lpt_get_iclkip(struct drm_i915_private *dev_priv)
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{
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struct iclkip_params p;
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u32 temp;
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if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
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return 0;
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iclkip_params_init(&p);
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mutex_lock(&dev_priv->sb_lock);
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temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
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if (temp & SBI_SSCCTL_DISABLE) {
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mutex_unlock(&dev_priv->sb_lock);
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return 0;
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}
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temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
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p.divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
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SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
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p.phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
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SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
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temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
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p.auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
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SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
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mutex_unlock(&dev_priv->sb_lock);
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p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc;
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return lpt_iclkip_freq(&p);
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}
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/* Implements 3 different sequences from BSpec chapter "Display iCLK
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* Programming" based on the parameters passed:
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* - Sequence to enable CLKOUT_DP
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* - Sequence to enable CLKOUT_DP without spread
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* - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
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*/
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static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
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bool with_spread, bool with_fdi)
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{
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u32 reg, tmp;
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if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
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"FDI requires downspread\n"))
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with_spread = true;
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if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
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with_fdi, "LP PCH doesn't have FDI\n"))
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with_fdi = false;
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mutex_lock(&dev_priv->sb_lock);
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tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
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tmp &= ~SBI_SSCCTL_DISABLE;
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tmp |= SBI_SSCCTL_PATHALT;
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intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
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udelay(24);
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if (with_spread) {
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tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
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tmp &= ~SBI_SSCCTL_PATHALT;
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intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
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if (with_fdi)
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lpt_fdi_program_mphy(dev_priv);
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}
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reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
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tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
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tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
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intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
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mutex_unlock(&dev_priv->sb_lock);
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}
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/* Sequence to disable CLKOUT_DP */
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void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
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{
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u32 reg, tmp;
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mutex_lock(&dev_priv->sb_lock);
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reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
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tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
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tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
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intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
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tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
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if (!(tmp & SBI_SSCCTL_DISABLE)) {
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if (!(tmp & SBI_SSCCTL_PATHALT)) {
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tmp |= SBI_SSCCTL_PATHALT;
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intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
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udelay(32);
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}
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tmp |= SBI_SSCCTL_DISABLE;
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intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
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}
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mutex_unlock(&dev_priv->sb_lock);
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}
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#define BEND_IDX(steps) ((50 + (steps)) / 5)
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static const u16 sscdivintphase[] = {
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[BEND_IDX( 50)] = 0x3B23,
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[BEND_IDX( 45)] = 0x3B23,
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[BEND_IDX( 40)] = 0x3C23,
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[BEND_IDX( 35)] = 0x3C23,
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[BEND_IDX( 30)] = 0x3D23,
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[BEND_IDX( 25)] = 0x3D23,
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[BEND_IDX( 20)] = 0x3E23,
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[BEND_IDX( 15)] = 0x3E23,
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[BEND_IDX( 10)] = 0x3F23,
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[BEND_IDX( 5)] = 0x3F23,
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[BEND_IDX( 0)] = 0x0025,
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[BEND_IDX( -5)] = 0x0025,
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[BEND_IDX(-10)] = 0x0125,
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[BEND_IDX(-15)] = 0x0125,
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[BEND_IDX(-20)] = 0x0225,
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[BEND_IDX(-25)] = 0x0225,
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[BEND_IDX(-30)] = 0x0325,
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[BEND_IDX(-35)] = 0x0325,
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[BEND_IDX(-40)] = 0x0425,
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[BEND_IDX(-45)] = 0x0425,
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[BEND_IDX(-50)] = 0x0525,
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};
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/*
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* Bend CLKOUT_DP
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* steps -50 to 50 inclusive, in steps of 5
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* < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
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* change in clock period = -(steps / 10) * 5.787 ps
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*/
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static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
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{
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u32 tmp;
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int idx = BEND_IDX(steps);
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if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
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return;
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if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
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return;
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mutex_lock(&dev_priv->sb_lock);
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if (steps % 10 != 0)
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tmp = 0xAAAAAAAB;
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else
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tmp = 0x00000000;
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intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
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tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
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tmp &= 0xffff0000;
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tmp |= sscdivintphase[idx];
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intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
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mutex_unlock(&dev_priv->sb_lock);
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}
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#undef BEND_IDX
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static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
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{
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u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
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u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
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if ((ctl & SPLL_PLL_ENABLE) == 0)
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return false;
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if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
|
|
(fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
|
|
return true;
|
|
|
|
if (IS_BROADWELL(dev_priv) &&
|
|
(ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
|
|
enum intel_dpll_id id)
|
|
{
|
|
u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
|
|
u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
|
|
|
|
if ((ctl & WRPLL_PLL_ENABLE) == 0)
|
|
return false;
|
|
|
|
if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
|
|
return true;
|
|
|
|
if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
|
|
(ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
|
|
(fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_encoder *encoder;
|
|
bool has_fdi = false;
|
|
|
|
for_each_intel_encoder(&dev_priv->drm, encoder) {
|
|
switch (encoder->type) {
|
|
case INTEL_OUTPUT_ANALOG:
|
|
has_fdi = true;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* The BIOS may have decided to use the PCH SSC
|
|
* reference so we must not disable it until the
|
|
* relevant PLLs have stopped relying on it. We'll
|
|
* just leave the PCH SSC reference enabled in case
|
|
* any active PLL is using it. It will get disabled
|
|
* after runtime suspend if we don't have FDI.
|
|
*
|
|
* TODO: Move the whole reference clock handling
|
|
* to the modeset sequence proper so that we can
|
|
* actually enable/disable/reconfigure these things
|
|
* safely. To do that we need to introduce a real
|
|
* clock hierarchy. That would also allow us to do
|
|
* clock bending finally.
|
|
*/
|
|
dev_priv->pch_ssc_use = 0;
|
|
|
|
if (spll_uses_pch_ssc(dev_priv)) {
|
|
drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
|
|
dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
|
|
}
|
|
|
|
if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
|
|
drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
|
|
dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
|
|
}
|
|
|
|
if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
|
|
drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
|
|
dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
|
|
}
|
|
|
|
if (dev_priv->pch_ssc_use)
|
|
return;
|
|
|
|
if (has_fdi) {
|
|
lpt_bend_clkout_dp(dev_priv, 0);
|
|
lpt_enable_clkout_dp(dev_priv, true, true);
|
|
} else {
|
|
lpt_disable_clkout_dp(dev_priv);
|
|
}
|
|
}
|
|
|
|
static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_encoder *encoder;
|
|
int i;
|
|
u32 val, final;
|
|
bool has_lvds = false;
|
|
bool has_cpu_edp = false;
|
|
bool has_panel = false;
|
|
bool has_ck505 = false;
|
|
bool can_ssc = false;
|
|
bool using_ssc_source = false;
|
|
|
|
/* We need to take the global config into account */
|
|
for_each_intel_encoder(&dev_priv->drm, encoder) {
|
|
switch (encoder->type) {
|
|
case INTEL_OUTPUT_LVDS:
|
|
has_panel = true;
|
|
has_lvds = true;
|
|
break;
|
|
case INTEL_OUTPUT_EDP:
|
|
has_panel = true;
|
|
if (encoder->port == PORT_A)
|
|
has_cpu_edp = true;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (HAS_PCH_IBX(dev_priv)) {
|
|
has_ck505 = dev_priv->display.vbt.display_clock_mode;
|
|
can_ssc = has_ck505;
|
|
} else {
|
|
has_ck505 = false;
|
|
can_ssc = true;
|
|
}
|
|
|
|
/* Check if any DPLLs are using the SSC source */
|
|
for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
|
|
u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
|
|
|
|
if (!(temp & DPLL_VCO_ENABLE))
|
|
continue;
|
|
|
|
if ((temp & PLL_REF_INPUT_MASK) ==
|
|
PLLB_REF_INPUT_SPREADSPECTRUMIN) {
|
|
using_ssc_source = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
"has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
|
|
has_panel, has_lvds, has_ck505, using_ssc_source);
|
|
|
|
/* Ironlake: try to setup display ref clock before DPLL
|
|
* enabling. This is only under driver's control after
|
|
* PCH B stepping, previous chipset stepping should be
|
|
* ignoring this setting.
|
|
*/
|
|
val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
|
|
|
|
/* As we must carefully and slowly disable/enable each source in turn,
|
|
* compute the final state we want first and check if we need to
|
|
* make any changes at all.
|
|
*/
|
|
final = val;
|
|
final &= ~DREF_NONSPREAD_SOURCE_MASK;
|
|
if (has_ck505)
|
|
final |= DREF_NONSPREAD_CK505_ENABLE;
|
|
else
|
|
final |= DREF_NONSPREAD_SOURCE_ENABLE;
|
|
|
|
final &= ~DREF_SSC_SOURCE_MASK;
|
|
final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
|
|
final &= ~DREF_SSC1_ENABLE;
|
|
|
|
if (has_panel) {
|
|
final |= DREF_SSC_SOURCE_ENABLE;
|
|
|
|
if (intel_panel_use_ssc(dev_priv) && can_ssc)
|
|
final |= DREF_SSC1_ENABLE;
|
|
|
|
if (has_cpu_edp) {
|
|
if (intel_panel_use_ssc(dev_priv) && can_ssc)
|
|
final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
|
|
else
|
|
final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
|
|
} else {
|
|
final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
|
|
}
|
|
} else if (using_ssc_source) {
|
|
final |= DREF_SSC_SOURCE_ENABLE;
|
|
final |= DREF_SSC1_ENABLE;
|
|
}
|
|
|
|
if (final == val)
|
|
return;
|
|
|
|
/* Always enable nonspread source */
|
|
val &= ~DREF_NONSPREAD_SOURCE_MASK;
|
|
|
|
if (has_ck505)
|
|
val |= DREF_NONSPREAD_CK505_ENABLE;
|
|
else
|
|
val |= DREF_NONSPREAD_SOURCE_ENABLE;
|
|
|
|
if (has_panel) {
|
|
val &= ~DREF_SSC_SOURCE_MASK;
|
|
val |= DREF_SSC_SOURCE_ENABLE;
|
|
|
|
/* SSC must be turned on before enabling the CPU output */
|
|
if (intel_panel_use_ssc(dev_priv) && can_ssc) {
|
|
drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
|
|
val |= DREF_SSC1_ENABLE;
|
|
} else {
|
|
val &= ~DREF_SSC1_ENABLE;
|
|
}
|
|
|
|
/* Get SSC going before enabling the outputs */
|
|
intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
|
|
intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
|
|
udelay(200);
|
|
|
|
val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
|
|
|
|
/* Enable CPU source on CPU attached eDP */
|
|
if (has_cpu_edp) {
|
|
if (intel_panel_use_ssc(dev_priv) && can_ssc) {
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
"Using SSC on eDP\n");
|
|
val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
|
|
} else {
|
|
val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
|
|
}
|
|
} else {
|
|
val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
|
|
}
|
|
|
|
intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
|
|
intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
|
|
udelay(200);
|
|
} else {
|
|
drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
|
|
|
|
val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
|
|
|
|
/* Turn off CPU output */
|
|
val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
|
|
|
|
intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
|
|
intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
|
|
udelay(200);
|
|
|
|
if (!using_ssc_source) {
|
|
drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
|
|
|
|
/* Turn off the SSC source */
|
|
val &= ~DREF_SSC_SOURCE_MASK;
|
|
val |= DREF_SSC_SOURCE_DISABLE;
|
|
|
|
/* Turn off SSC1 */
|
|
val &= ~DREF_SSC1_ENABLE;
|
|
|
|
intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
|
|
intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
|
|
udelay(200);
|
|
}
|
|
}
|
|
|
|
drm_WARN_ON(&dev_priv->drm, val != final);
|
|
}
|
|
|
|
/*
|
|
* Initialize reference clocks when the driver loads
|
|
*/
|
|
void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
|
|
{
|
|
if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
|
|
ilk_init_pch_refclk(dev_priv);
|
|
else if (HAS_PCH_LPT(dev_priv))
|
|
lpt_init_pch_refclk(dev_priv);
|
|
}
|