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e563531ace
Split out the display register helper macros to a separate file. For now, include it from i915_reg.h, but note that there are already files that don't need i915_reg.h, such as intel_audio.c. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3af47193ff5219b6d2cfe353b752ec4bb44de4f1.1668008071.git.jani.nikula@intel.com
75 lines
2.9 KiB
C
75 lines
2.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_SNPS_PHY_REGS__
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#define __INTEL_SNPS_PHY_REGS__
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#include "intel_display_reg_defs.h"
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#define _SNPS_PHY_A_BASE 0x168000
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#define _SNPS_PHY_B_BASE 0x169000
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#define _SNPS_PHY(phy) _PHY(phy, \
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_SNPS_PHY_A_BASE, \
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_SNPS_PHY_B_BASE)
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#define _SNPS2(phy, reg) (_SNPS_PHY(phy) - \
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_SNPS_PHY_A_BASE + (reg))
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#define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
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#define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
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(reg) + (ln) * 0x10))
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#define SNPS_PHY_MPLLB_CP(phy) _MMIO_SNPS(phy, 0x168000)
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#define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
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#define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
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#define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
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#define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
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#define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
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#define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
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#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
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#define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
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#define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
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#define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
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#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
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#define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
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#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
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#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
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#define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
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#define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
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#define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
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#define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
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#define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
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#define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
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#define SNPS_PHY_MPLLB_FRACN2(phy) _MMIO_SNPS(phy, 0x16800C)
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#define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
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#define SNPS_PHY_MPLLB_FRACN_QUOT REG_GENMASK(15, 0)
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#define SNPS_PHY_MPLLB_SSCEN(phy) _MMIO_SNPS(phy, 0x168014)
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#define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
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#define SNPS_PHY_MPLLB_SSC_UP_SPREAD REG_BIT(30)
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#define SNPS_PHY_MPLLB_SSC_PEAK REG_GENMASK(29, 10)
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#define SNPS_PHY_MPLLB_SSCSTEP(phy) _MMIO_SNPS(phy, 0x168018)
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#define SNPS_PHY_MPLLB_SSC_STEPSIZE REG_GENMASK(31, 11)
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#define SNPS_PHY_MPLLB_DIV2(phy) _MMIO_SNPS(phy, 0x16801C)
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#define SNPS_PHY_MPLLB_HDMI_PIXEL_CLK_DIV REG_GENMASK(19, 18)
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#define SNPS_PHY_MPLLB_HDMI_DIV REG_GENMASK(17, 15)
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#define SNPS_PHY_MPLLB_REF_CLK_DIV REG_GENMASK(14, 12)
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#define SNPS_PHY_MPLLB_MULTIPLIER REG_GENMASK(11, 0)
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#define SNPS_PHY_REF_CONTROL(phy) _MMIO_SNPS(phy, 0x168188)
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#define SNPS_PHY_REF_CONTROL_REF_RANGE REG_GENMASK(31, 27)
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#define SNPS_PHY_TX_REQ(phy) _MMIO_SNPS(phy, 0x168200)
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#define SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR REG_GENMASK(31, 30)
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#define SNPS_PHY_TX_EQ(ln, phy) _MMIO_SNPS_LN(ln, phy, 0x168300)
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#define SNPS_PHY_TX_EQ_MAIN REG_GENMASK(23, 18)
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#define SNPS_PHY_TX_EQ_POST REG_GENMASK(15, 10)
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#define SNPS_PHY_TX_EQ_PRE REG_GENMASK(7, 2)
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#endif /* __INTEL_SNPS_PHY_REGS__ */
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