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dde01ed5b0
Follow the new direction for debugfs files, moving the details where the implementation is. It seems quite natural skl_watermark.c is the place that controls IPC details, even for debugfs, not intel_display_debugfs.c. Rename the functions and convert dev_priv->i915 while at it. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9d59b18f5dc06e86a48c1ce0f40d625f51e3e85a.1662983005.git.jani.nikula@intel.com
80 lines
2.6 KiB
C
80 lines
2.6 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __SKL_WATERMARK_H__
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#define __SKL_WATERMARK_H__
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#include <linux/types.h>
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#include "intel_display.h"
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#include "intel_global_state.h"
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#include "intel_pm_types.h"
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_bw_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_plane;
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u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915);
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
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void intel_sagv_post_plane_update(struct intel_atomic_state *state);
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bool intel_can_enable_sagv(struct drm_i915_private *i915,
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const struct intel_bw_state *bw_state);
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u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915,
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const struct skl_ddb_entry *entry);
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void skl_write_plane_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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void skl_write_cursor_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
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const struct skl_ddb_entry *entries,
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int num_entries, int ignore_idx);
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void skl_wm_get_hw_state(struct drm_i915_private *i915);
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void skl_wm_sanitize(struct drm_i915_private *i915);
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void intel_wm_state_verify(struct intel_crtc *crtc,
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struct intel_crtc_state *new_crtc_state);
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void skl_watermark_ipc_init(struct drm_i915_private *i915);
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void skl_watermark_ipc_update(struct drm_i915_private *i915);
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bool skl_watermark_ipc_enabled(struct drm_i915_private *i915);
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void skl_watermark_ipc_debugfs_register(struct drm_i915_private *i915);
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void skl_wm_init(struct drm_i915_private *i915);
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struct intel_dbuf_state {
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struct intel_global_state base;
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struct skl_ddb_entry ddb[I915_MAX_PIPES];
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unsigned int weight[I915_MAX_PIPES];
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u8 slices[I915_MAX_PIPES];
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u8 enabled_slices;
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u8 active_pipes;
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bool joined_mbus;
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};
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struct intel_dbuf_state *
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intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
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#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
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#define intel_atomic_get_old_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
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#define intel_atomic_get_new_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
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int intel_dbuf_init(struct drm_i915_private *i915);
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void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
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void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
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void intel_mbus_dbox_update(struct intel_atomic_state *state);
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#endif /* __SKL_WATERMARK_H__ */
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