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6ece49c569
Enabling the SPI CS35L41 audio codec driver for Steam Deck [1]
revealed a problem with the current AMD SPI controller driver
implementation, consisting of an unrecoverable system hang.
The issue can be prevented if we ensure the max transfer size
and the max message size do not exceed the FIFO buffer size.
According to the implementation of the downstream driver, the
AMD SPI controller is not able to handle more than 70 bytes per
transfer, which corresponds to the size of the FIFO buffer.
Hence, let's fix this by setting the SPI limits mentioned above.
[1] https://lore.kernel.org/r/20220621213819.262537-1-cristian.ciocaltea@collabora.com
Reported-by: Anastasios Vacharakis <vacharakis@o2mail.de>
Fixes: bbb336f39e ("spi: spi-amd: Add AMD SPI controller driver support")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20220706100626.1234731-2-cristian.ciocaltea@collabora.com
Signed-off-by: Mark Brown <broonie@kernel.org>
350 lines
8.4 KiB
C
350 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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//
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// AMD SPI controller driver
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//
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// Copyright (c) 2020, Advanced Micro Devices, Inc.
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//
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// Author: Sanjay R Mehta <sanju.mehta@amd.com>
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#include <linux/acpi.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/spi/spi.h>
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#include <linux/iopoll.h>
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#define AMD_SPI_CTRL0_REG 0x00
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#define AMD_SPI_EXEC_CMD BIT(16)
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#define AMD_SPI_FIFO_CLEAR BIT(20)
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#define AMD_SPI_BUSY BIT(31)
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#define AMD_SPI_OPCODE_REG 0x45
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#define AMD_SPI_CMD_TRIGGER_REG 0x47
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#define AMD_SPI_TRIGGER_CMD BIT(7)
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#define AMD_SPI_OPCODE_MASK 0xFF
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#define AMD_SPI_ALT_CS_REG 0x1D
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#define AMD_SPI_ALT_CS_MASK 0x3
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#define AMD_SPI_FIFO_BASE 0x80
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#define AMD_SPI_TX_COUNT_REG 0x48
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#define AMD_SPI_RX_COUNT_REG 0x4B
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#define AMD_SPI_STATUS_REG 0x4C
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#define AMD_SPI_FIFO_SIZE 70
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#define AMD_SPI_MEM_SIZE 200
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/* M_CMD OP codes for SPI */
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#define AMD_SPI_XFER_TX 1
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#define AMD_SPI_XFER_RX 2
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enum amd_spi_versions {
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AMD_SPI_V1 = 1, /* AMDI0061 */
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AMD_SPI_V2, /* AMDI0062 */
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};
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struct amd_spi {
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void __iomem *io_remap_addr;
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unsigned long io_base_addr;
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enum amd_spi_versions version;
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};
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static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
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{
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return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
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}
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static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
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{
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iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
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}
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static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
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{
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u8 tmp = amd_spi_readreg8(amd_spi, idx);
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tmp = (tmp & ~clear) | set;
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amd_spi_writereg8(amd_spi, idx, tmp);
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}
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static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
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{
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return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
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}
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static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
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{
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iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
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}
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static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
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{
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u32 tmp = amd_spi_readreg32(amd_spi, idx);
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tmp = (tmp & ~clear) | set;
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amd_spi_writereg32(amd_spi, idx, tmp);
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}
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static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs)
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{
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amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK);
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}
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static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select)
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{
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amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK);
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}
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static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi)
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{
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amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR);
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}
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static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode)
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{
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switch (amd_spi->version) {
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case AMD_SPI_V1:
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amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode,
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AMD_SPI_OPCODE_MASK);
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return 0;
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case AMD_SPI_V2:
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amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode);
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return 0;
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default:
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return -ENODEV;
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}
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}
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static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
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{
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amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
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}
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static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
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{
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amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
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}
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static int amd_spi_busy_wait(struct amd_spi *amd_spi)
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{
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u32 val;
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int reg;
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switch (amd_spi->version) {
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case AMD_SPI_V1:
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reg = AMD_SPI_CTRL0_REG;
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break;
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case AMD_SPI_V2:
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reg = AMD_SPI_STATUS_REG;
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break;
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default:
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return -ENODEV;
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}
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return readl_poll_timeout(amd_spi->io_remap_addr + reg, val,
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!(val & AMD_SPI_BUSY), 20, 2000000);
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}
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static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
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{
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int ret;
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ret = amd_spi_busy_wait(amd_spi);
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if (ret)
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return ret;
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switch (amd_spi->version) {
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case AMD_SPI_V1:
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/* Set ExecuteOpCode bit in the CTRL0 register */
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amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
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AMD_SPI_EXEC_CMD);
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return 0;
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case AMD_SPI_V2:
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/* Trigger the command execution */
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amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG,
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AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD);
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return 0;
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default:
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return -ENODEV;
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}
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}
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static int amd_spi_master_setup(struct spi_device *spi)
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{
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struct amd_spi *amd_spi = spi_master_get_devdata(spi->master);
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amd_spi_clear_fifo_ptr(amd_spi);
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return 0;
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}
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static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
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struct spi_master *master,
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struct spi_message *message)
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{
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struct spi_transfer *xfer = NULL;
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u8 cmd_opcode;
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u8 *buf = NULL;
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u32 m_cmd = 0;
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u32 i = 0;
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u32 tx_len = 0, rx_len = 0;
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list_for_each_entry(xfer, &message->transfers,
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transfer_list) {
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if (xfer->rx_buf)
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m_cmd = AMD_SPI_XFER_RX;
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if (xfer->tx_buf)
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m_cmd = AMD_SPI_XFER_TX;
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if (m_cmd & AMD_SPI_XFER_TX) {
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buf = (u8 *)xfer->tx_buf;
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tx_len = xfer->len - 1;
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cmd_opcode = *(u8 *)xfer->tx_buf;
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buf++;
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amd_spi_set_opcode(amd_spi, cmd_opcode);
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/* Write data into the FIFO. */
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for (i = 0; i < tx_len; i++) {
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iowrite8(buf[i], ((u8 __iomem *)amd_spi->io_remap_addr +
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AMD_SPI_FIFO_BASE + i));
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}
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amd_spi_set_tx_count(amd_spi, tx_len);
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amd_spi_clear_fifo_ptr(amd_spi);
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/* Execute command */
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amd_spi_execute_opcode(amd_spi);
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}
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if (m_cmd & AMD_SPI_XFER_RX) {
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/*
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* Store no. of bytes to be received from
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* FIFO
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*/
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rx_len = xfer->len;
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buf = (u8 *)xfer->rx_buf;
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amd_spi_set_rx_count(amd_spi, rx_len);
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amd_spi_clear_fifo_ptr(amd_spi);
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/* Execute command */
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amd_spi_execute_opcode(amd_spi);
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amd_spi_busy_wait(amd_spi);
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/* Read data from FIFO to receive buffer */
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for (i = 0; i < rx_len; i++)
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buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i);
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}
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}
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/* Update statistics */
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message->actual_length = tx_len + rx_len + 1;
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/* complete the transaction */
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message->status = 0;
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switch (amd_spi->version) {
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case AMD_SPI_V1:
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break;
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case AMD_SPI_V2:
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amd_spi_clear_chip(amd_spi, message->spi->chip_select);
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break;
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default:
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return -ENODEV;
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}
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spi_finalize_current_message(master);
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return 0;
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}
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static int amd_spi_master_transfer(struct spi_master *master,
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struct spi_message *msg)
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{
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struct amd_spi *amd_spi = spi_master_get_devdata(master);
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struct spi_device *spi = msg->spi;
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amd_spi_select_chip(amd_spi, spi->chip_select);
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/*
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* Extract spi_transfers from the spi message and
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* program the controller.
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*/
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amd_spi_fifo_xfer(amd_spi, master, msg);
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return 0;
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}
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static size_t amd_spi_max_transfer_size(struct spi_device *spi)
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{
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return AMD_SPI_FIFO_SIZE;
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}
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static int amd_spi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct spi_master *master;
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struct amd_spi *amd_spi;
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int err = 0;
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/* Allocate storage for spi_master and driver private data */
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master = spi_alloc_master(dev, sizeof(struct amd_spi));
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if (!master) {
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dev_err(dev, "Error allocating SPI master\n");
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return -ENOMEM;
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}
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amd_spi = spi_master_get_devdata(master);
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amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(amd_spi->io_remap_addr)) {
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err = PTR_ERR(amd_spi->io_remap_addr);
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dev_err(dev, "error %d ioremap of SPI registers failed\n", err);
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goto err_free_master;
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}
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dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);
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amd_spi->version = (enum amd_spi_versions) device_get_match_data(dev);
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/* Initialize the spi_master fields */
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master->bus_num = 0;
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master->num_chipselect = 4;
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master->mode_bits = 0;
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master->flags = SPI_MASTER_HALF_DUPLEX;
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master->setup = amd_spi_master_setup;
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master->transfer_one_message = amd_spi_master_transfer;
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master->max_transfer_size = amd_spi_max_transfer_size;
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master->max_message_size = amd_spi_max_transfer_size;
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/* Register the controller with SPI framework */
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err = devm_spi_register_master(dev, master);
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if (err) {
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dev_err(dev, "error %d registering SPI controller\n", err);
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goto err_free_master;
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}
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return 0;
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err_free_master:
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spi_master_put(master);
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return err;
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}
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#ifdef CONFIG_ACPI
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static const struct acpi_device_id spi_acpi_match[] = {
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{ "AMDI0061", AMD_SPI_V1 },
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{ "AMDI0062", AMD_SPI_V2 },
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{},
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};
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MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
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#endif
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static struct platform_driver amd_spi_driver = {
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.driver = {
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.name = "amd_spi",
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.acpi_match_table = ACPI_PTR(spi_acpi_match),
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},
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.probe = amd_spi_probe,
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};
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module_platform_driver(amd_spi_driver);
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
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MODULE_DESCRIPTION("AMD SPI Master Controller Driver");
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